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cml microcircuits communication semiconductors CMX885 marine vhf audio and signalling processor d/885/3 december 2010 audio and signalling processing, dtmf, dsc/atis and noaa with auxiliary functions for use in marine vhf systems features ? concurrent audio/signalling/data operations ? dual auxiliary adc, 4 multiplexed inputs ? complete audio-band processing: o selectable audio processing order o pre and de-emphasis o selectable 2.55/3.0 khz filtering o limiter ? 4 x auxiliary dacs ? dual programmable system clock outputs ? tx outputs for single, two-point modulation ? 3 x analogue inputs (mic or discriminator) ? dsc/atis modem for marine applications ? programmable voice scrambler ? digital gain adjustment ? inband signalling: dtmf, noaa nwr ? c-bus serial interface to host controller ? default 3.6864mhz xtal/clock ? dtmf and audio tone encoder/decoder ? flexible powersave modes ? small vqfn and lqfp packages ? low-power 3.0v to 3.6v operation modulator rf (rx/tx) discriminator host c auxiliary multiplexed adc inputs CMX885 marine vhf baseband processor ? cml microsystems plc 2010 rx enable tx enable irq c-bus system clock 1 reference clock 3v to 3.6v supply system clock 2 auxiliary dacs mic input audio out discriminator optional 2 nd receiver rf (rx) 1 brief description the CMX885 is a half-duplex, audio, signalling and dat a processing ic for use in marine vhf radio systems. comprehensive audio processing facilities include comp lete audio processing, filtering, pre- or de- emphasis and frequency inversion scrambling. signal rout ing and filtering is included to assist host c based signal encoding/decoding applications. 1200bps digital selcall (dsc) or automatic transmitter i dentification system (atis) modem with protocol support and nwr decoding are supported. a dtmf encoder/decoder, a full complement of aux iliary adcs and dacs and dual synthesised clock outputs are included in this low power pmr processor. the device also has flexible powersaving modes and is available in 48-pin vqfn and lqfp packages.
marine vhf audio and signalling processor CMX885 ? cml microsystems plc 2 2010 d/885/3 contents section page 1 brief descr iption.............................................................................................................. .......1 1.1 history........................................................................................................................ ..5 2 block di agram .................................................................................................................. ......6 3 signal and pin list ............................................................................................................ .....7 3.1 signal defi nitions.........................................................................................................9 4 external component s ..........................................................................................................10 5 pcb layout guidelines and power supply d ecouplin g...................................................12 6 general d escripti on ............................................................................................................ .13 7 detailed d escripti ons.......................................................................................................... .14 7.1 device ident code .....................................................................................................14 7.2 xtal fr equency ..........................................................................................................14 7.3 host inte rface ............................................................................................................14 7.4 device c ontrol ...........................................................................................................16 7.4.1 signal rout ing .....................................................................................................16 7.4.2 mode cont rol .......................................................................................................17 7.5 audio func tions .........................................................................................................18 7.5.1 audio receiv e mode ...........................................................................................18 7.5.2 audio transmi t mode ..........................................................................................20 7.6 inband signa lling .......................................................................................................23 7.6.1 receiving dt mf t ones.......................................................................................23 7.6.2 transmitting dt mf t ones...................................................................................23 7.7 dsc modem - (fsk 1200bps ) ..................................................................................24 7.7.1 receiving ds c signal s .......................................................................................25 7.7.2 transmitting ds c signal s ...................................................................................26 7.8 noaa/nwr same and wat dec oding ..................................................................27 7.8.1 message code format ........................................................................................28 7.8.2 wat detect ion ....................................................................................................29 7.8.3 same dec oding ..................................................................................................29 7.9 auxiliary adc operatio n ...........................................................................................29 7.10 auxiliary dac/ramd ac operat ion...........................................................................30 7.11 digital system cl ock gener ator ................................................................................31 7.11.1 main clock o peratio n .........................................................................................31 7.11.2 system clock operatio n .....................................................................................32 7.12 gpio..........................................................................................................................3 2 7.13 signal level op timisati on ..........................................................................................32 7.13.1 transmit path levels ..........................................................................................32 7.13.2 receive path levels ...........................................................................................32 7.14 c-bus inte rface ........................................................................................................33 7.14.1 interrupt o peration..............................................................................................33 7.14.2 general no tes .....................................................................................................33 8 configurati on guide............................................................................................................ .34
marine vhf audio and signalling processor CMX885 ? cml microsystems plc 3 2010 d/885/3 8.1 c-bus register summa ry ........................................................................................34 8.1.1 reset oper ations.................................................................................................35 8.1.2 general reset ? $01 writ e...................................................................................35 8.1.3 auxadc and tx mod m ode ? $a7 wr ite ............................................................36 8.1.4 auxdac control/data ? $a8 wr ite ......................................................................37 8.1.5 auxadc1 data ? $a9 r ead..................................................................................38 8.1.6 auxadc2 data ? $aa r ead .................................................................................38 8.1.7 sysclk1 and sysclk2 pll data ? $ab, $ad write .......................................39 8.1.8 sysclk1 and sysclk2 ref ? $ac and $ae write .........................................39 8.1.9 analogue output gain ? $b0 wr ite......................................................................40 8.1.10 input gain and output signal routing ? $b 1 write.............................................41 8.1.11 reserved ? $b 2 write..........................................................................................41 8.1.12 reserved ? $b 3 write..........................................................................................41 8.1.13 reserved ? $b4 8-bit r ead ..................................................................................41 8.1.14 auxadc threshold data ? $b5 wr ite .................................................................42 8.1.15 reserved ? $b 6 write..........................................................................................42 8.1.16 nwr status and data ? $bb read .....................................................................42 8.1.17 powerdown control ? $c0 wr ite .........................................................................42 8.1.18 mode control ? $c1 writ e ...................................................................................43 8.1.19 audio control ? $c2 writ e ...................................................................................44 8.1.20 tx inband tones ? $c3 writ e..............................................................................44 8.1.21 rx data 1 ? $c5 r ead .........................................................................................44 8.1.22 status ? $c 6 read ...............................................................................................45 8.1.23 modem configurati on ? $c7 wr ite ......................................................................46 8.1.24 programming register ? $c8 wr ite.....................................................................46 8.1.25 tx data 1 ? $ca writ e.........................................................................................46 8.1.26 tone status ? $cc r ead .....................................................................................47 8.1.27 audio tone ? $cd writ e......................................................................................48 8.1.28 interrupt mask ? $ce writ e .................................................................................50 8.1.29 reserved ? $c f write .........................................................................................50 8.2 programming register operat ion..............................................................................51 8.2.1 program block 0 ? modem configur ation ...........................................................52 8.2.2 program block 1 ? inband tone se tup ...............................................................53 8.2.3 program block 2 ? reserv ed ................................................................................53 8.2.4 program block 3 ? auxdac, ra mdac and clock control ................................53 8.2.5 program block 4 ? gain and offset setup ..........................................................54 8.2.6 initialisation of t he program blocks .....................................................................58 9 performance sp ecificatio n ..................................................................................................59 9.1 electrical pe rformanc e ..............................................................................................59 9.1.1 absolute maxi mum rati ngs.................................................................................59 9.1.2 operating limits ..................................................................................................59 9.1.3 operating charac teristics ....................................................................................60 9.1.4 parametric pe rformanc e......................................................................................65 9.2 c-bus ti ming............................................................................................................67 9.3 packagi ng..................................................................................................................68 table page table 1 definition of power supply and refer ence volt ages......................................................... 9
marine vhf audio and signalling processor CMX885 ? cml microsystems plc 4 2010 d/885/3 table 2 xtal/clock frequency setti ngs for program block 3 ........................................................ 14 table 3 dtmf tone pa irs....................................................................................................... ...... 24 table 4 rese t operat ions ...................................................................................................... ....... 35 table 5 voice lev el attenuation ............................................................................................... .... 49 table 6 program block selection............................................................................................... ... 51 table 7 ramd ac va lues ......................................................................................................... .... 54 figure page figure 1 bl ock di agram .................................................................................................................. 6 figure 2 recommended external co mponents ........................................................................... 10 figure 3 power supply and de-coup ling ...................................................................................... 12 figure 4 c-bu s transac tions ................................................................................................... .... 15 figure 5 signal routing ....................................................................................................... ......... 17 figure 6 rx 25khz channel audio filter frequency respons e................................................... 19 figure 7 de-emphasis curve for tia/eia-603 complianc e.......................................................... 19 figure 8 tx channel audio filter response and temp late (etsi) .............................................. 21 figure 9 tx channel audio filter response and temp late (tia) ................................................ 21 figure 10 audio fr equency pre-em phasis ................................................................................... 22 figure 11 ds c form at .......................................................................................................... ......... 24 figure 12 dsc c haracter format ................................................................................................ ... 25 figure 13 digital clo ck generation schemes ............................................................................... 31 figure 14 level adjustments ................................................................................................... ..... 33 figure 15 limi ter va lues ...................................................................................................... ......... 56 figure 16 default tx audio filter line-up ..................................................................................... 57 figure 17 default rx audio filter line-up..................................................................................... 57 figure 18 preferred tx audio filter line- up ................................................................................. 57 figure 19 preferred rx audio filter line- up ................................................................................. 57 figure 20 c- bus ti ming........................................................................................................ ....... 67 figure 21 mechanical outli ne of 48-pin vq fn (q 3)..................................................................... 68 figure 22 mechanical outline of 48-pin lq fp ( l4) ...................................................................... 68 it is always recommended that you check for the late st product datasheet version from the cml website: [ www.cmlmicro.com ].
marine vhf audio and signalling processor CMX885 ? cml microsystems plc 5 2010 d/885/3 1.1 history version changes date 3 ? clarified operation of data end bit (b7) for dsc rx mode in section 8.1.22. ? clarified the need for observing c-bus la tency when writing multiple c-bus commands in section 7.3. ? minor typographical corrections in tabl e of section 8.1.27, p4.10 and p4.11 values in section 8.2.5. 20/12/201 0 2 ? changed "modem control" to "modem cofiguration" register ? bit references changed to "$c1: b12" style, for consistency ? changed name of $c1:b2 to "modem enable" and $c!:b4 to "modem source" ? deleted other references to "processing" in the description of $c1 register bits ? deleted the reference to "clearing the e n_dsc bit" at the end of section 7.7.1 ? xtal frequency tolerance in section 9.1.4 changed from 100ppm to 30ppm, to meet dsc specifications. ? corrected dac3 to dac4 in figure 1. ? +1db and 3db limits apply to all rx and tx responses (figures 6 to 10). wording changed accordingly in section 7.5. ? "write" added to description of audio tone register ($cd) in section 7.6. ? reference in $c1 to bits 11-9 should read 11-8 in section 7.6. ? program block registers p3.2 to p3.6 s hould read p3.2 - p3.7 in section 7.11.1. ? gpio rxena and txena signals - nomenclature standardised in section 7.12. ? hyperlink added for $c1 in section 8.1. ? correction of $c0 b6 to "bias bl ock enable" in section 8.1.17. ? merge table rows for $ce b9 in section 8.1.28. ? removed references to msk: these should be dsc in sections 7.7.1 and 7.7.2. ? clarification of status register bit 3, modem control register bits 3-8 and bit 11, interrupt mask register bits 3 and 5. ? footnotes in parametric specificati ons harmonised with table references. ? minor typographical corrections. 8/4/2010 1 ? this document created ? based on 7041fi-1.x documentation 18/9/2009
marine vhf audio and signalling processor CMX885 2 block diagram auxiliary systems control systems core operations and routing rx audio processing disc alt mic voice filter de-emphasis de-scrambler voice filter pre-emphasis scrambler channel filter tx audio processing fsk demodulator dsc atis noaa same rx processing dtmf decoder mod1 mod2 audio (sections can be de-selected and processing order is programmable) (sections can be de-selected and processing order is programmable) v bias fsk modulator dsc atis v bias dacs dac 1 dac 2 dac 3 dac 4 ramp profile ram dac outputs adc inputs adc 1 adc 2 adcs system clocks synthesised clocks level thresholds averaging configured io digital io sysclk1 txena rxena sysclk2 mux level thresholds averaging irqn rdata cdata csn sclk c-bus interface crystal oscillator main pll and dividers xtaln xtal/clk registers dvdd dvss vdec avdd avss vbias power control regulator bias soft limiter analogue routing v bias mux mod mode mux mux mux mux mux filter audio tones dtmf encoder in-band signalling and data tx processing mux nwr detection figure 1 block diagram ? cml microsystems plc 6 2010 d/885/3
marine vhf audio and signalling processor CMX885 ? cml microsystems plc 7 2010 d/885/3 3 signal and pin list 48-pin l4/q3 pin name type description 1 - nc reserved ? leave unconnected 2 - nc reserved ? leave unconnected 3 - nc reserved ? leave unconnected 4 - nc reserved ? leave unconnected 5 - nc reserved ? leave unconnected 6 - nc reserved ? leave unconnected 7 dvss pwr digital ground 8 irqn op c-bus: a 'wire-orable' output for connection to the interrupt request input of the host. pulled down to dv ss when active and is high impedance when inactive. an external pull-up resistor (r1) is required. 9 vdec pwr internally generated 2.5v digi tal supply voltage. must be decoupled to dv ss by capacitors mounted close to the device pins. no other connections allowed. 10 rxena op rx enable ? active lo w when in rx mode ($c1:b0 = 1) 11 - nc reserved ? leave unconnected 12 - nc reserved ? leave unconnected 13 sysclk1 op synthesised digital system clock output 1 14 dvss pwr digital ground 15 txena op tx enable ? active low when in tx mode ($c1:b1 = 1) 16 discn ip discriminator inverting input 17 discfb op discriminator input amplifier feedback 18 altn ip alt inverting input 19 altfb op alt input amplifier feedback 20 micfb op mic input amplifier feedback 21 micn ip mic inverting input 22 avss pwr analogue ground 23 mod1 op modulator 1 output 24 mod2 op modulator 2 output 25 vbias op internally generated bias voltage of about av dd /2, except when the device is in ?powersave? mode when v bias will discharge to av ss . must be decoupled to av ss by a capacitor mounted close to the device pi ns. no other connections allowed. 26 audio op audio output 27 adc1 ip auxiliary adc input (1) 28 adc2 ip auxiliary adc input (2) 29 adc3 ip auxiliary adc input (3)
marine vhf audio and signalling processor CMX885 ? cml microsystems plc 8 48-pin l4/q3 pin name type description 2010 d/885/3 30 adc4 ip auxiliary adc input (4) 31 avdd pwr positive 3.3v supply rail for the analogue on-chip circuits. levels and thresholds within the device are proportional to this voltage. this pin should be decoupled to av ss by capacitors mounted close to the device pins. 32 dac1 op auxiliary dac output 1/ramdac 33 dac2 op auxiliary dac output 2 34 avss pwr analogue ground 35 dac3 op auxiliary dac output 3 36 dac4 op auxiliary dac output 4 37 dvss pwr digital ground 38 vdec pwr internally generated 2.5v s upply voltage. must be decoupled to dv ss by capacitors mounted close to the device pins. no other connections allowed. 39 xtal/clk ip input to the oscillator inverter fr om the xtal circuit or external clock source. 40 xtaln op the output of the on-ch ip xtal oscillator inverter 41 dvdd pwr the 3.3v positive supply rail for the digital on-chip circuits. this pin should be decoupled to dvss by capacitors mounted close to the device pins 42 cdata ip c-bus: serial data input from the c 43 rdata ts op c-bus: a 3-state c-bus serial data output to the c. this output is high impedance when not sending data to the c. 44 - nc reserved ? do not connect this pin 45 dvss pwr digital ground 46 sclk ip c-bus: the c-bus serial clock input from the c 47 sysclk2 op synthesised digital system clock output 2 48 csn ip c-bus: the c-bus chip select input from the c - there is no internal pullup on this input e xposed m etal p ad substrate ~ on this device, the central metal pad (which is exposed on q3 packages only) may be electrically unconnected or, alternatively, may be connected to analogue ground (avss). no other electrical connections are permitted. notes: ip = input (+ pu/pd = inte rnal pullup/pulldown resistor) op = output bi = bidirectional ts op = 3-state output pwr = power connection nc = no connection - should not be connected to any signal
marine vhf audio and signalling processor CMX885 ? cml microsystems plc 9 2010 d/885/3 3.1 signal definitions table 1 definition of power supply and reference voltages signal name pins usage av dd avdd power supply for analogue circuits dv dd dvdd power supply for digital circuits v dec vdec power supply for core logic, derived from dv dd by on-chip regulator v bias vbias internal analogue reference level, derived from av dd av ss avss ground for all analogue circuits dv ss dvss ground for all digital circuits
marine vhf audio and signalling processor CMX885 4 external components figure 2 recommended external components r1 100k c1 18pf c11 see note 5 c21 10nf r2 100k c2 18pf c12 180pf c22 10nf r3 100k c3 10nf c13 see note 5 c23 10nf r4 100k c4 not used c14 180pf c24 10f r5 see note 2 c5 1nf c15 see note 5 r6 100k c6 100pf c16 180pf r7 see note 3 c7 100nf c17 10f r8 100k c8 100pf c18 10nf x1 3.6864mhz r9 see note 4 c9 100pf c19 10nf see note 1 r10 100k c10 not used c20 10f resistors 5%, capacitors and inductors 20% unless otherwise stated. ? cml microsystems plc 10 2010 d/885/3
marine vhf audio and signalling processor CMX885 ? cml microsystems plc 11 2010 d/885/3 notes: 1. x1 can be a crystal or an external clock gener ator; this will depend on the application. the tracks between the crystal and the device pins should be as short as possible to achieve maximum stability and best start up performance. by default, a 3.6864mhz clock is selected, other values could be used if the various internal clock di viders are set to appropriate values. 2. r5 should be selected to provide the desired dc gain (assuming c11 is not present) of the discn input, as follows: ? gain discn ? = 100k / r5 the gain should be such that the re sultant output at the discfb pin is within the input signal range specified in 7.13.2 . 3. r7 should be selected to provide the desired dc gain (assuming c13 is not present) of the altn input as follows: ? gain altn ? = 100k / r7 the gain should be such that the re sultant output at the altfb pin is within the input signal range specified in 7.13. 4. r9 should be selected to provide the desired dc gain (assuming c15 is not present) of the micn input as follows: ? gain micn ? = 100k / r9 the gain should be such that the re sultant output at the micfb pin is within the input signal range specified in 7.13.1 . for optimum performance with low signal microphones, an additional external gain stage may be required. 5. c11, c13 and c15 should be selected to maintain the lower frequency roll-off of the micn, altn and discn inputs as follows: c11 100nf ? gain discn ? c13 100nf ? gain altn ? c15 30nf ? gain micn ? 6. altn and altfb connections allow the user to have an additional signal input. component connections and values are as for the respective discn and micn networks. if this input is not required, the altn pin should be connected to avss. 7. c5 (audio output) should be increased to 1. 0f if frequencies below 300hz need to be used on this pin. 8. a single 10f electrolytic capacitor (c24, fi tted as shown) may be used for smoothing the power supply to both vdec pins, providing they are connected together on the pcb with an adequate width power supply trace. alternativ ely, separate smoothing capacit ors should be connected to each vdec pin. high frequency decoupling capacitors (c3 and c23) must always be fitted as close as possible to both vdec pins.
marine vhf audio and signalling processor CMX885 5 pcb layout guidelines and power supply decoupling figure 3 power supply and de-coupling component values as per figure 2 . notes: it is important to protect the analogue pins from extraneous inband noise and to minimise the impedance between the device and the supply and bias de-coupling capacitors. the de-coupling capacitors c3, c7, c18, c19, c21, c22, c24 and c25 should be as cl ose as possible to the device. it is therefore recommended that the printed circuit board is la id out with separate ground planes for the av ss and dv ss supplies in the area of the cmx 885, with provision to make links between them, close to the device. use of a multi-layer printed circuit board will facilitate the provision of ground planes on separate layers. v bias is used as an internal reference for detecti ng and generating the various analogue signals. it must be carefully decoupled, to ensure its integrity, so apart from the decoupling capacitor shown, no other loads should be connected. if v bias needs to be used to set the discriminat or mid-point reference, it must be buffered with a high input impedance buffer. the single-ended microphone input and audio output must be ac coupled (as shown), so that their return paths can be connected to av ss without introducing dc offsets. fu rther buffering of the audio output is advised. the crystal x1 may be replaced with an external clock source. ? cml microsystems plc 12 2010 d/885/3
marine vhf audio and signalling processor CMX885 ? cml microsystems plc 13 2010 d/885/3 6 general description the CMX885 is intended for use in half duplex analogue two-way mobile radio equipment and is particularly suited to the marine vhf band. the cm x885 provides signal filtering, encoder and decoder functions for audio, inband tones, dtmf, nwr and dsc/at is, permitting simple to sophisticated levels of tone control and data transfer. a flexible power cont rol facility allows the device to be placed in its optimum powersave mode when not actively processing signals. the CMX885 includes a crystal clock generator, with a buffered output, to provide a common system clock if required. a block diagram of the CMX885 is shown in figure 1 . the signal processing blocks can be individually assigned to either of two signal processing paths, which in turn, can be routed from any of the three audio/discrim inator input pins. this allows for a very flexible routing architecture and allows the facility for di fferent processing blocks to act on different analogue inputs. for marine use, it would be typical to route rx audi o from the working channel receiver through from the discn input, while at the same time routing the dsc/atis fsk modem from the dsc channel 70 receiver from the altn input. tx functions: o single/dual microphone inputs with input am plifier and programmable gain adjustment o filtering selectable for 12.5khz and 25khz channels o selectable pre-emphasis o selectable frequency inversion voice scrambling o selectable audio processing order o two-point modulation outputs with programmable level adjustment o programmable audio tone generator (for custom audio tones) o programmable dtmf generator o tx enable output o 1200bps fsk modem for dsc/atis use (to itu-r m.493-11) rx functions: o single/dual demodulator inputs with input amplifier and programmable gain adjustment o audio-band and sub-audio rejection filtering o selectable de-emphasis o selectable frequency inversion voice de-scrambling o selectable audio processing order o software volume control o dtmf decoder o rx enable output o 1200bps fsk modem for dsc/atis use (to itu-r m.493-11) o nwr same and wat detector auxiliary functions: o 2 programmable system clock outputs o 2 auxiliary adcs with selectable input paths o 4 auxiliary dacs, one with built-in programmable ramdac interface: o c-bus, 4 wire high speed synchronous serial command/data bus o open drain irq to host
marine vhf audio and signalling processor CMX885 ? cml microsystems plc 14 2010 d/885/3 7 detailed descriptions 7.1 device ident code following a power-on or reset (see section 8.1.1 ), the device will report the device ident code in the tone status register ($cc) to indicate that it is operational. 7.2 xtal frequency the CMX885 is designed to work with a xtal of 3.6864m hz. if this default configuration is not used, then program block 3 (see section 8.2.4 ) should be loaded with the correct va lues to ensure that the device will work to specification with t he user specified clock frequency. a table of common values can be found in table 2. note the maximum xtal frequency is 12.288mhz, although an external clock source of up to 24.576mhz can be used. the register values in table 1 are shown in hex (however only the lo wer 10 bits are relevant), the default settings are shown in bold, and the settings which do not give an exact setting (but are within acceptable limits) are in italics. the new p3.2-3 settings take e ffect following the write to p3.3 (the settings in p3.4-7 are implemented on a change to rx or tx mode). table 2 xtal/clock frequency settings for program block 3 program block external frequency source (mhz) 3.6864 6.144 9.216 12.0 12.8 16.368 16.8 19.2 p3.2 gp timer $01c $018 $018 $019 $019 $018 $019 $018 p3.3 idle vco output and aux clk divide $084 $088 $08c $10f $110 $095 $115 $099 p3.4 ref clk divide $030 $040 $060 $07d $0c8 $155 $15e $0c8 p3.5 pll clk divide $280 $200 $200 $200 $300 $400 $400 $200 p3.6 vco output and aux clk divide $13c $140 $140 $140 $140 $140 $140 $140 p3.7 rx or tx internal adc / dac clk divide $008 $008 $008 $008 $008 $008 $008 $008 7.3 host interface a serial data interface (c-bus) is used for comm and, status and data transfe rs between the CMX885 and the host c; this interface is compatible with mi crowire and spi. interrupt signals notify the host c when a change in status has occurred and the c should read the status register across the c-bus and respond accordingly. interrupts only occur if the appropriate mask bit has been set. see section 7.14.1 . the CMX885 will monitor the state of the c-bus registers that the hos t has written to every 250s (the c- bus latency period) hence it is not advisable for the host to make successive writes to the same c-bus register within this period. to minimise activity on the c-bus interface, optim ise response times and ensure reliable data transfers, it is advised that the irq facility be utilised (using the ir q mask register, $ce). it is permissible for the host to poll the irq pin if the host c does not support a fu lly interrupt-driven architecture. this removes the need to continually poll the c-bus status register ($c6) for status changes. the c-bus block provides for the transfer of dat a and control or status information between the CMX885?s internal registers and the hos t c over the c-bus serial interf ace. each transaction consists of a single address byte sent from the c which may be followed by one or more data byte(s) sent from the c to be written into one of the CMX885?s write only registers, or one or more data byte(s) read out from one of the CMX885?s read only registers, as illustrated in figure 4 . data sent from the c on the cdata line is clo cked into the CMX885 on the rising edge of the sclk input. rdata sent from the CMX885 to the c is va lid when sclk is high. the csn line must be held
marine vhf audio and signalling processor CMX885 ? cml microsystems plc 15 2010 d/885/3 low during a data transfer and kept high between transfers . the c-bus interface is compatible with most common c serial interfaces and may also be eas ily implemented with general purpose c i/o pins controlled by a simple software routine. the number of data bytes following an address byte is dependent on the value of the address byte. the most significant bits of the address or data ar e sent first. for detailed timings see section 9.2 . note that, due to internal timing constraints, there may be a delay of up to 250s between the end of a c-bus write operation and the device reading the data fr om its internal register. ensure that this c-bus latency time (up to 250s) is observed when writing multip le commands to the same c-bus register. c-bus write: see note 1 see note 2 csn sclk cdata 7 6 5 4 3 2 1 0 7 6 ? 0 7 ? 0 msb lsb msb lsb msb lsb address/command byte upper 8 bits lower 8 bits rdata high z state c-bus read: see note 2 csn sclk cdata 7 6 5 4 3 2 1 0 msb lsb address byte upper 8 bits lower 8 bits rdata 7 6 ? 0 7 ? 0 high z state msb lsb msb lsb data value unimportant repeated cycles either logic level valid (and may change) either logic level valid (but must not change from low to high) figure 4 c-bus transactions notes: 1. for command byte transfers only the fi rst 8 bits are transferred ($01 = reset). 2. for single byte data transfers only the first 8 bits of the data are transferred. 3. the cdata and rdata lines are never active at the same time. the address byte determines the data direction for each c-bus transfer. 4. the sclk input can be high or low at the start and end of each c-bus transaction. 5. the gaps shown between each byte on the cda ta and rdata lines in the above diagram are optional, the host may insert gaps or concatenate the data as required.
marine vhf audio and signalling processor CMX885 ? cml microsystems plc 16 2010 d/885/3 7.4 device control the CMX885 can be set into many modes to suit the environment in which it is to be used. these modes are described in the following sections and are programm ed over the c-bus: either directly to operational registers or, for parameters that are not likely to change during operation, via the programming register ($c8). for basic operation: 1. enable the relevant hardware sections via the power down control register 2. set the appropriate mode registers to t he desired state (audio, inband, data, etc.) 3. select the required signal routing and gain 4. use the mode control register to place the device into rx or tx mode to conserve power when the devic e is not actively processing an analogue signal, place the device into idle mode. additional powersaving can be achieved by disabling the unused hardware blocks, however, care must be taken not to disturb any sect ions that are automatically controlled. see: o powerdown control ? $c0 write o mode control ? $c1 write 7.4.1 signal routing the CMX885 offers a very flexible routing architec ture, with three signal inputs, two separate signal processing paths and two modulator outputs (to su it 2-point modulation schemes) and a single audio output. each of the signalling processing blocks c an be independently routed from either of the input blocks, which can be routed from any of the three input signal pins. the audio/voice processing blocks are always routed from input 1. the outputs from signal processing blocks are determined by the settings of the auxadc and tx mod mode register in tx mode. see: o input gain and output signal routing ? $b1 write o auxadc and tx mod mode ? $a7 write o mode control ? $c1 write
marine vhf audio and signalling processor CMX885 formatted mode dsc modem bpf data modem in-band signalling dtmf de- emphasis de- scrambler channel filter audio processing receive functions alt i/p mic i/p disc i/p vbias hpf mux $c1 b11 hpf audio routing $b1 b6 vbias vbias input 2 $b1 b15-13 input 1 $b1 b12-10 raw mode mux $c1 b4 mux $b1 b3,2 mux $b1 b5,4 audio gain $b0 b3-0 data modem scrambler inband signalling programmable tone dtmf audio processing transmit functions pre- emphasis channel filtering soft limiter tx mod mode $a7 b12,13 mux $c1 b14-2 raw mode dsc modem output 1 output 2 formatted mode mod2 gain $b0 b10-8 mod1 gain $b0 b14-11 mux $b1 b9,8 mux $b1 b7 output 1 mux $c1 b13 bpf modem nwr modem figure 5 signal routing the analogue gain/attenuation of each input and output can be set individually, with additional fine gain control available via the programming register. see: o analogue output gain ? $b0 write o input gain and output signal routing ? $b1 write 7.4.2 mode control the CMX885 operates in one of three modes: o idle o rx o tx at power-on or following a reset, the device will autom atically enter idle mode, which allows for the maximum powersaving whilst still retaining the capabilit y of monitoring the four adc inputs (if enabled). it is only possible to write to the progra mming register whilst in idle mode. see: o mode control ? $c1 write ? cml microsystems plc 17 2010 d/885/3
marine vhf audio and signalling processor CMX885 ? cml microsystems plc 18 2010 d/885/3 7.5 audio functions the audio signal can be processed in several wa ys, depending on the implementation required, by selecting the relevant bits in the audio control ? $c2 write register. in both rx and tx modes, a selectable channel filter to suit either the 12.5khz or 25khz tia/etsi channel mask can be selected. this filter also incorporates a soft limiter to reduce the effects of over-modulation. other features include pre- and de-emphasis, 300hz hpf and frequency inversion scram bling, all of which may be individually enabled 1 . the order in which these features are exec uted is selectable to ensure compatibility with existing implementations and provi de optimal performance (see section 8.2.5 ). 7.5.1 audio receive mode the CMX885 operates in half duplex, so whilst in receive mode the transmit path (microphone input and modulator output amplifiers) can be disabled and pow ered down if required. the audio output signal level is equalised (to v bias ) before switching between the audio port and the modulator ports, to minimise unwanted audible transients. the off/powersave level of the modulator outputs is the same as the vbias pin, so the audio output level must also be at this level before switching. see: o audio control ? $c2 write receiving audio band signals when a voice-based signal is being received, it is up to the host c, in response to signal status information provided by the CMX885, to control mu ting/enabling of the audio signal to the audio output. the discriminator path through the device has a progr ammable gain stage. whilst in receive mode this should normally be set to 0db (the default) gain. receive filtering the incoming signal is filtered, as shown in figure 6 (with the 300hz hpf also active), to remove sub- audio components and to minimise high frequency noise. when appropriate, the audio signal can then be routed to the audio output. separate se lectable filters are available for: ? 300hz high pass ? 2.55khz low pass (for 12.5khz channel operation) ? 3.0khz low pass (for 25khz channel operation) note that with no filters selected, the low frequency response ex tends to below 5hz at the low end but still rolls off above 3.3khz at the top end. in figure 6 and figure 7 , the template shows the +1 and -3db limits. 1 the typical responses shown in , , , were recorded using the pe0201 evkit, disc to audio and mod1 out. figure 6 figure 7 figure 8 figure 9
marine vhf audio and signalling processor CMX885 250 250 3000 3000 2550 2550 300 300 -40 -35 -30 -25 -20 -15 -10 -5 0 5 10 15 10 1000 frequency (hz) db (ref 1khz) all filters off - $0000 hpf & 25k filter - $0c00 template figure 6 rx 25khz channel audio filter frequency response 250 250 3000 3000 2550 2550 300 300 -40 -35 -30 -25 -20 -15 -10 -5 0 5 10 15 10 1000 frequency (hz) db (ref 1khz) de-emp & 12.5k - $3000 de-emp & 12.5k & hpf - $3400 template figure 7 de-emphasis curve for tia/eia-603 compliance ? cml microsystems plc 19 2010 d/885/3
marine vhf audio and signalling processor CMX885 ? cml microsystems plc 20 2010 d/885/3 de-emphasis optional de-emphasis at -6db per oc tave from 300hz to 3000hz (shown in figure 7 ) can be selected, to facilitate compliance with tia/eia-603, en 300 086, en 301 025. audio de-scrambling the CMX885 incorporates an optional frequency inve rsion de-scrambler in receive mode. this de- scrambles received audio band signal s that have been scrambled in the transmitter. the inversion frequency defaults to 3300hz, but may be modified by writing to p4.8. see: o audio control ? $c2 write 7.5.2 audio transmit mode the device operates in half duplex, so when in transmit mode the receive path (discriminator and audio output amplifiers) should be disabled, and can be powered down, by the host c. two modulator outputs with independently programmable gains are provided to facilitate single or two- point modulation. if one of the modulator outputs is not used it can be dis abled to conserve power. to avoid spurious transmissions when changing from rx to tx, the mod1 and mod2 outputs are ramped to the quiescent modulator output level, v bias before switching (if enabled by b7 of the analogue gain register, $b0). similarly, when starting a transmi ssion, the transmitted signal is ramped up from the quiescent v bias level and when ending a transmission the transmitted signal is ramped down to the quiescent v bias level. the ramp rates are set in the pr ogram block p4.6. when the modulator outputs are disabled, their outputs will be set to v bias . when the modulator output drivers are powered down, their outputs will be floating (high impedance), so the rf modulator will need to be turned off. for all transmissions, the host c must only enable signals after the appropriate data and settings for those signals are loaded into the c-bus registers. as soon as any signalling is enabled the CMX885 will use the settings to control the way information is transmitted. a programmable gain stage in the microphone input path facilitates a host controlled vogad capability, or an internal agc function may be used. see: o audio control ? $c2 write o auxadc and tx mod mode ? $a7 write o input gain and output signal routing ? $b1 write processing audio signals for transmission over analogue channels the microphone input(s), with programmable gain, can be selected as the audio input source. pre- emphasis is selectable with either of the two analogue tx audio filters (for 12.5khz and 25khz channel spacing). these are designed for use in en 300 086, tia/eia-603 or en 301 025 compliant applications. when the 300hz hpf is enabled, it will attenuate frequencies below 250hz by more than 33db with respect to the signal level at 1khz. in figure 8 , figure 9 and figure 10 , the template shows the +1 and -3db limits. these filters, together with a built in limiter , help ensure compliance with en 300 086 and en 301 025 (25khz and 12.5khz channel spacing) when levels and gain settings are set up correctly in the target system.
marine vhf audio and signalling processor CMX885 ? cml microsystems plc 21 2010 d/885/3 250 250 3000 3000 2550 2550 300 300 -40 -35 -30 -25 -20 -15 -10 -5 0 5 10 15 10 1000 frequency (hz) db (ref 1khz) tx all filters off - $0000 hpf & 12.5k filter - $1400 template 25k filter - $0800 figure 8 tx channel audio filter response and template (etsi) 250 250 3000 3000 2550 2550 300 300 -40 -35 -30 -25 -20 -15 -10 -5 0 5 10 15 10 1000 frequency (hz) db (ref 1khz) tx all filters off - $0000 hpf & 12.5k filter - $1400 template 25k filter - $0800 figure 9 tx channel audio filter response and template (tia)
marine vhf audio and signalling processor CMX885 the characteristics of the 12.5khz channel filter fit the template shown in figure 8 and figure 9 . this filter also facilitates implementation of systems compliant with ti a/eia-603 ?a? , ?b? and ?c? bands . the CMX885 provides selectable pr e-emphasis filtering of +6db per octave from 300hz to 3000hz, matching the template shown in figure 10 . 250 250 3000 3000 2550 2550 300 300 -40 -35 -30 -25 -20 -15 -10 -5 0 5 10 15 10 1000 frequency (hz) db (ref 1khz) pre-emp & 12.5k & hpf - $3400 pre-emp & 25k & hpf - $2c00 template figure 10 audio frequency pre-emphasis modulator output routing the tx signal can be routed to both mod1 and mod2 outputs in accordance with the settings of: o auxadc and tx mod mode ? $a7 write o input gain and output signal routing ? $b1 write input agc an automatic gain control system can be enabled by se tting the relevant bits of the program block p4.9. the setting of the input 1 gain stage is recor ded when the device enters tx mode and if the signal exceeds the pre-set threshold, the input 1 gain is aut omatically reduced in 3.2db steps until it falls within the operational levels or the range of the gain stage is exhausted. when the signal level drops, the gain will be automatically increased in 3.2db steps at t he rate set in p4.9 until the initial value has been reached. for maximum effect the system should be des igned such that the +22.4db setting of the input 1 gain stage achieves the nominal levels. to ensure c onsistent operation, it is recommended that the input 1 gain stage value be re-initialised before entering tx mode. the signal that is used as an input to this process can be selected to be either the: ? output of input1 gain stage ? output of the pre-emphasis filter by selecting the relevant bit in p4.9. the pre-em phasis option should only be chosen if this block is actually in use. o input gain and output signal routing ? $b1 write o program block 4 ? gain and offset setup ? cml microsystems plc 22 2010 d/885/3
marine vhf audio and signalling processor CMX885 ? cml microsystems plc 23 2010 d/885/3 audio scrambling the CMX885 incorporates an optional frequency inversi on scrambler in transmit mode. this scrambles audio band signals, to be de-scrambled in the receiver . the inversion frequency defaults to 3300hz, but maybe modified by writing to p4.8. see: o audio control ? $c2 write 7.6 inband signalling the CMX885 supports dcs, nwr (rx only) and dtmf signalling and a user-programmable audio tone generator (288hz to 3000hz). note that if tones below 400hz are used, the 300hz hpf should be disabled. selection of the inband signalling mode is performed by bi ts 11-8 of the mode regist er ($c1). detection of the selected inband signalling mode can be performed in parallel with voice or data reception. see: o mode control ? $c1 write o tx inband tones ? $c3 write o tone status ? $cc read o audio tone ? $cd write 7.6.1 receiving dtmf tones dtmf tone detection may be enabled in the mode regi ster ($c1) in parallel with other inband tone modes (however, this is not recommended due to t he increased likelihood of false detects). when a dtmf tone has been detected, b10 of t he tone status register ($cc) and b12 of the irq status register, $c6, will be set. this value will overwrite any exis ting inband tone value that may be present. the dtmf detector returns the values shown below in table 3. 7.6.2 transmitting dtmf tones the dtmf signals to be generated are defined in the tx tone register ($c3). single tones and twist (lower frequency tone reduced by 2db) can be enabled by se tting the appropriate bit in the $c3 register to 1. the dtmf level is set in program block p1.0. the dtmf tones must be transmitted on their own, the host c must disable audio band signals prior to in itiating transmission of the dtmf tones and (if required) restore the audio band signals after the dtmf transmission is complete. table 3 shows the dtmf tone pairs, together with the values for progra mming the ?tone pair? field of the txtone register.
marine vhf audio and signalling processor CMX885 ? cml microsystems plc 24 2010 d/885/3 table 3 dtmf tone pairs tone code (hex) key pad position low tone (hz) high tone (hz) 1 1 697 1209 2 2 697 1336 3 3 697 1477 4 4 770 1209 5 5 770 1336 6 6 770 1477 7 7 852 1209 8 8 852 1336 9 9 852 1477 a 0 941 1336 b * 941 1209 c # 941 1477 d a 697 1633 e b 770 1633 f c 852 1633 0 d 941 1633 note: only the underlined tone is generat ed when the 'single tone' bit is enabled. 7.7 dsc modem - (fsk 1200bps) the device can implement a 1200 bps dsc (digital selective call) modem conforming to the requirements of itu-r m.493-11 for use in marine vh f band radio equipment. this modem uses tones at 1300hz and 2100hz to represent binary 1?s and 0?s respec tively, with 6db/octave pre-emphasis in tx. see: o mode control ? $c1 write o modem configuration ? $c7 write o rx data 1 ? $c5 o tx data 1 ? $ca write dx/rx a b c d e f g h i format specifier called party address category self- identification tele- command message frequency message frequency message end of sequence error-check character dot pattern phasing sequence 2 identical characters 5 characters 1 character 5 characters 2 characters 3 characters 3 characters 3 identical dx characters 1 rx character 1 character d x d x d x d x d x d x a a b l b 2 b 3 r 4 b 5 c d l d 2 d 3 d 4 d 5 e l e 2 f l f 2 f 3 g l g 2 g 3 h i h h dot pattern r x 7 r x 6 r x 5 r x 4 r x 3 r x 2 r x 1 r x 0 a a b l b 2 b 3 b 4 b 5 c d 1 d 2 d 3 d 4 d 5 e l e 2 f l f 2 f 3 g l g 2 g 3 h i figure 11 dsc format to enable this mode, the en_dsc bit of the modem configuration register $c7:b11 must be set. the dsc modem itself can then be cont rolled by setting or clearing the modem enable bit $c1:b2, after
marine vhf audio and signalling processor CMX885 ? cml microsystems plc 25 2010 d/885/3 selecting the appropriate source with $c1:b4. note that, due to the c-bus latency times, there should be a delay after clearing this bit, before re-enabling it again. with dsc mode selected $c7:b8 to b3 and $c7:b1 to b0 are ignored. two modes of operation are provided: o raw mode o formatted mode s y m bol e m itted s ignal s y m bol e m itted s ignal s y m bol e m itted s ignal no. and bit p osition no. and bit p osition no. and bit p osition 12345678910 12345678910 12345678910 00 bbbbbbby y y 43 yyb yb yb b y y 86 b yyb yb yb yy 01 ybbbbbbyyb 44 bbyybybybb 87 yyybybybyb 02 bybbbbbyyb 45 ybyybybby y 88 bbbyybyybb 03 yybbbbbyb y 46 byyybybby y 89 ybbyybyby y 04 bbybbbbyyb 47 yyyybybbyb 90 bybyybyby y 05 ybybbbbyb y 48 bbbbyybyb y 91 yybyybybyb 06 byybbbbyb y 49 ybbbyybybb 92 bby y ybyby y 07 yyybbbbybb 50 bybbyybybb 93 ybyyybybyb 08 bbbybbbyyb 51 yybbyybby y 94 byyyybybyb 09 ybbybbbyb y 52 bbybyybybb 95 yyyyybybb y 10 bybybbbyb y 53 ybybyybby y 96 bbbbbyyyb y 11 yybybbbybb 54 byybyybby y 97 ybbbbyyybb 12 bbyybbbyb y 55 yyybyybbyb 98 b y bbbyyybb 13 ybyybbbybb 56 bbbyyybybb 99 yybbbyyby y 14 byyybbbybb 57 ybbyyybby y 100 bbybbyyybb 15 yyyybbbby y 58 bybyyybby y 101 ybybbyyby y 16 bbbbybbyyb 59 yybyyybbyb 102 byybbyyby y 17 ybbbybbyb y 60 bbyyyybby y 103 yyybbyybyb 18 bybbybbyb y 61 ybyyyybbyb 104 bbbybyyybb 19 yybbybbybb 62 byyyyybbyb 105 ybbybyyby y 20 bbybybbyb y 63 yyyyyybbb y 106 bybybyyby y 21 ybybybbybb 64 bbbbbbyyyb 107 yybybyybyb 22 byybybbybb 65 ybbbbbyyb y 108 bbyybyyby y 23 yyyby bbby y 66 bybbbbyyb y 109 ybyybyybyb 24 bbbyybbyb y 67 y y bbbbyybb 110 byyybyybyb 25 ybbyybbybb 68 bbybbbyyb y 111 yyyybyybb y 26 bybyybbybb 69 ybybbbyybb 112 bbbbyyyybb 27 yybyybbby y 70 byybbbyybb 113 ybbbyyyby y 28 bbyyybbybb 71 yyybbbyby y 114 bybbyyyby y 29 ybyyybbby y 72 bbbybbyyb y 115 yybbyyybyb 30 byyyy bbby y 73 ybbybbyybb 116 bbybyyyby y 31 yyyyy bbbyb 74 bybybbyybb 117 ybybyyybyb 32 bbbbbybyyb 75 yybybbyby y 118 byybyyybyb 33 ybbbbybyb y 76 bbyybbyybb 119 yyybyyybb y 34 bybbbybyb y 77 ybyybbyby y 120 bbbyyyyby y 35 yybbbybybb 78 byyybbyby y 121 ybbyyyybyb 36 bbybbybyb y 79 yyyybbybyb 122 bybyyyybyb 37 ybybbybybb 80 bbbbybyyb y 123 yybyyyybb y 38 byybbybybb 81 ybbbybyybb 124 bbyyyyybyb 39 yyybbybby y 82 bybbybyybb 125 ybyyyyybb y 40 bbbybybyb y 83 yybbybyby y 126 byyyyyybb y 41 ybbybybybb 84 bbybybyybb 127 yyyyyy y bbb 42 bybybybybb 85 ybybybyby y b = 0 y = 1 order of transmitted bits: bit 1 first figure 12 dsc character format 7.7.1 receiving dsc signals the received signal is filtered and data is extracted with the aid of a p ll to recover the clock from the serial data stream. the recovered data is stored in a 2-byte buffer (grouped into 16-bit words) and an interrupt issued to indicate received data is ready . data is transferred over the c-bus under host c control. if this data is not read bef ore the next data is decoded it will be ov erwritten and it is up to the user to ensure that the data is transferred at an adequate rate following data ready being flagged. the dsc bit clock is not output externally.
marine vhf audio and signalling processor CMX885 ? cml microsystems plc 26 2010 d/885/3 the extracted data is compared with the 16-bit programmed frame sync pattern (preset to $cb23 following a reset command). an interrupt will be fl agged when the programmed frame sync pattern is detected. the host c may stop the frame sync s earch by disabling the dsc demodulator ($c1:b2 cleared to 0). once a valid frame sync pattern has been detected, the frame sync search algorithm is disabled; it may be re-started by the host disabling the modem enable bit of the mode control register ($c1:b2) and then re-enabling it (taki ng note of the c-bus latency time). in rx raw mode (en_raw=1) the modem will report back all data received as soon as it is enabled. (note: if a valid dsc signal is not present when the modem is first enabled, it will still attempt to demodulate the input signal and output data. the host must determine if the data is valid or not. it is possible to use the sync facility to reduce the amount of invalid data presented to the host, but this may also lead to dsc calls with errors in the sync pattern being missed). as soon as the modem enable bit has been asserted, the modem will attempt to demodulate the input signal. data bits will then be delivered to the rx data 1 register, $c5 as they are demodulated, indicated by the data_rdy bit. it is up to the host to ali gn, decode and validate the data and to subsequently switch the modem off once an eos (end of sequence) has been detected (by clearing $c1:b2 to 0). in this mode, the device does not perform byte alignment or phasing (synchronisation) detection 2 . the host must read the rxdata 1 register before t he next 16 bits of data hav e been received, otherwise the data will be lost. if the sync facility is used in raw mode, then the va lue of sync must be programmed by the host to a suitable value via the program blocks, p0.0 and p0 .1. the values $5555 or $aaaa are suggested for this setting, however, this will not completely remove false detections and the following received data must be analysed before assuming that a valid call is in pr ogress (see itu-r m.493-11 for details). the sync enable bit $c7:b15 must be asserted. setting the modem enable bit $c1:b2 will activate the dsc modem, which will then attempt to decode the signal at its input. acquisition of the sync data pattern will be reported to the host by the se tting of the dsc bit $c6:b3. in rx formatted mode, (en_raw=0) the modem will check the incoming bit stream for a valid sequence of phasing characters (3x rx, 2x dx+ rx or dx + 2 x rx) and then report any correctly decoded characters in the rxdata1 ($c5) register. the characte rs are packed into the 16-bit register as two 7-bit characters and an additional error indication bit (bits 15 and 7). in the case where an odd number of characters has been received, the unused field will be reported as 0000000. this mechanism significantly reduces the amount of data transferred to t he host and the host processing requirements. the decoded 7-bit characters will be delivered to the rxdata1 register, $c5, as indicated by the data_rdy bit. the modem will not report valid data until it has correctly re ceived the initial phasing sequence. once the phasing sequence has been detect ed, the modem?s internal dpll bandwidth will be automatically reduced to improve the error performance. if one of the time-d iversity received characters is in error, only the correct one will be reported. if both characters have errors, the last one received will be reported, with bit 7 (msb) set. the characters reported back will correspond to the data sequence (see figure 11 ) 3 : a a b1 b2 b3 b4 b5 c d1 d2 d3 d4 d5 e1 e2 f1 f2 f3 g1 g2 g3 h i once the h and i fields have been received by the host, it should shut the dsc modem down by clearing the modem enable bit in the m ode control register $c1:b2. 7.7.2 transmitting dsc signals the dsc encoding operates in accordance with the bi t settings in the modem configuration register ($c7). when enabled the modulator will begin transmitting data using the settings and values in program block 0 (bit sync and frame sync patterns), the modem configuration register and the tx data registers. therefore, these registers should be programmed to the required values before transmission is enabled. 2 this is similar to the fx 604, cmx910 and cmx7032 operation. 3 this particular sequence corresponds to the exampl e given in itu-r m493-11. different telecommands will produce different sequenc es of varying lengths.
marine vhf audio and signalling processor CMX885 ? cml microsystems plc 27 2010 d/885/3 the CMX885 generates its own internal data clock and converts the binary data into the appropriately phased frequencies. the binary data is taken from tx data 1 register ($ca), most significant bit first. in tx raw mode (en_raw=1) the host must supply all data to be transmitted by the modem via the txdata register ($ca) in the correct order and format to conform to the dsc standards. setting the modem enable bit $c1:b2, will enable t he dsc modem, which will then transmit the data supplied by the host through the tx data 1 register , $ca. the modem configuration register $c7:b10 should also be set to enable/disable raw data mode, as appropriate. in tx formatted mode (en_raw=0), the modem will aut omatically transmit the dotting pattern followed by the phasing sequence and then encode the data presented at the tx data 1 register ($ca) with the correct checksum bits and then transmit it in the correct position with automatic repetition to conform to the time diversity requirements of t he standard. data in the tx data 1 register is presented as two 7-bit characters, in the case where an odd number of char acters needs to be sent, then the un-used character should be set to 0000000 and b7 set to 1. the final characters sent by the host should be a valid ?end-of- sequence? character followed by the ?error check? character. valid dsc characters should be supplied by the host th rough the tx data 1 register, $ca. two characters can be loaded in the same c-bus write operati on. the modem will begin transmitting the dotting sequence followed by the phasing sequence as soon as the modem enable bit $c1:b2 is set. the format of the data supplied by the host is similar to the rx format: a a b1 b2 b3 b4 b5 c d1 d2 d3 d4 d5 e1 e2 f1 f2 f3 g1 g2 g3 h i there is no facility for automatically generating cont inuous dotting (preamble), y data (all 1?s), b data (all 0?s) or phasing (synchronisation) sequences interna lly, however, the modem will continue to transmit the last data loaded into the txdata1 register, so only a single data load is required. 7.8 noaa/nwr same and wat decoding a data decoder and tone detector suitable for use with the noaa?s nwr (noaa weather radio) system is provided in the device. full deta ils of the system are publicly av ailable from the noaa website at http://www.nws.noaa.gov/nwr/ and the CMX885 provides support for the wat detection and same decoding. it is possible to route the signal input to eit her input 1 or input 2 so that nwr monitoring can be performed in parallel with existing radio operations (subject to suitable rf sections being provided externally). see: o nwr status and data ? $bb read o mode control ? $c1 write o status ? $c6 read o modem configuration ? $c7 write o interrupt mask ? $ce the nwr same data message consists of six possible elements in the following sequence: 1 preamble 2 header code 3 warning alarm tone/attention signal 4 voice message 5 preamble 6 end of message (eom) elements 1, 2, 5 and 6 will always be transmitt ed in an nwr same message and repeated three times. elements 3 and 4 may or may not be transmitted depending on the specific type of message or its application. the coded message is transmitted, using frequency sh ift keying (fsk), in the nwr audio channel. in this application and the implementation currently used by the fcc eas, it is more accurate to refer to the code format as audio frequency shift keying (afsk). it is transmitted at no less than 80% modulation ( 4.0khz deviation minimum, 5.0khz deviation maximum).
marine vhf audio and signalling processor CMX885 ? cml microsystems plc 28 2010 d/885/3 the coded message and voice message is transmitted ov er the nwr transmitter network using standard pre-emphasis for narrow band vhf frequency modulation (f m) of 6db per octave increasing slope from 300hz to 3,000hz applied to the modulator. preamble. the preamble and header code are transmitted three times with a one second pause ( 5%) between each coded message burst prior to the broadc ast of the actual voice message. then the preamble and end of message (eom) code are transmitted three times with a one second pause ( 5%) between each eom burst. preamble byte. the first 16 bytes (prior to the header code and eom) of the data transmission constitute a preamble with each byte having the value $ab (8 bit byte [10101011]). for all byte s, the least significant bit (lsb) is sent first. the bytes following the pream ble constitute the actual message data transmission. note: for nwr system maintenance, nws will occasi onally send a continuous string of preamble code, $ab or a continuous tone through its communications links to the nwr transmitters, for several seconds up to around one minute. bit definition. the following definitions of a bit are bas ed on a bit period equaling 1920 microseconds ( one microsecond). o the data rate is 520.83 bits per second o logic zero is 1562.5 hz. o logic one is 2083.3 hz o mark and space bit periods are equal at 1.92 milliseconds. header. bit and byte synchronization is attained by the preamble code at the beginning of each header code or eom data transmission. the message data (header) code is transmitted using american standard code for information interchange (ascii) char acters as defined in ansi incits 4 (rev 86, 2002), with the eighth bit always set to zero. each separate header code data transmission should not exceed a total of 268 bytes if the maximum allowable geographic locations (31) are included. warning alarm tone. the warning alarm tone (wat), if transmitted, is sent within one to three seconds following the third header code burst. the frequency of t he wat is 1050hz (0.3%) for 8 to 10 seconds at no less than 80% modulation (4.0 khz deviati on minimum, 5.0 khz deviation maximum). voice message . if transmitted, the actual voiced message begins within three to five seconds following the last nwr same code burst or wat, whichev er is last. the voice audio ranges between 20% modulation ( 1 khz deviation) and 90% modulation ( 4.5 khz deviation) with occasional lulls near zero and peaks as high as, but not exceeding, 100% modulation ( 5.0 khz devia tion). total length of the voice message should not exceed two minutes. preamble . a repeat of above. end of message . eom is identified by the use of ?nnnn.? 7.8.1 message code format (preamble) zczc-org-eee-pssccc-pss ccc+tttt-jjjhhmm-llllllll- (1 second pause) (preamble) zczc-org-eee-pssccc-pss ccc+tttt-jjjhhmm-llllllll- (1 second pause) (preamble) zczc-org-eee-pssccc-pssccc+tttt- jjjhhmm-llllllll- (1 to 3 second pause) 1050 hz warning alarm tone for 8 to 10 seconds ? (if transmitted) (3 to 5 second pause) voice /spoken oral text of message ? (if transmitted) (1 to 3 second pause) (preamble) nnnn (1 second pause) (preamble) nnnn (1 second pause) (preamble) nnnn
marine vhf audio and signalling processor CMX885 ? cml microsystems plc 29 2010 d/885/3 7.8.2 wat detection the wat detector is enabled by setting the nwr bit $c1:b12 and indicated by setting b15 of the nwrdata register ($bb). if enabled, the nwr irq bit in the status register $c6:b14 will also be set. the detector will be reset after 500ms, so multiple detections may be indicated on long wat tones. 7.8.3 same decoding the same data is received at 520.83bps and decoded by the CMX885 whenever the nwr bit $c1:b12 is set. internally, the CMX885 monitors the selected input until it detects the preamble sequence and then passes the subsequently recovered data to the host uc via the nwr data register ($bb). the decoder will detect the data header and determine if it is ?zczc? indicating that data follows or ?nnnn? indicating the end of a transmission and report these states in bits 13 and 14 of the nwr data register ($bb) respectively). if enabled, the nwr irq bit in the st atus register $c6:b14 will also be set following the detection of the preamble and on ev ery subsequently received byte. when the en_nwr_data bit is set, the receiver outputs the received bitstream. the host is allowed to set this bit at any time to get "raw mode" data output with no preamble/header detection and no guarantee of byte alignment. when the en_nwr_data bit is clear, the receiver searches for a valid same transmission but does not output data. if it sees a preamble followed by the data header ("zczc"), it raises an irq and *automatically* sets the en_nwr_data bit to put itself into data-output mode. it is then up to the host to decide when to clear the en_nwr_data bit to put t he receiver back into sync-search mode (thus "re- arming" it). if the receiver sees a preamble followed by the end-of-message header ("nnnn") while doing sync- search, it informs the host [2] and then continues the search without putting itself into data-output mode. it is the responsibility of the host to shut the decoder down at the end of a received burst by clearing the en_nwr_data bit $c7:b12 to 0. 7.9 auxiliary adc operation the input to the auxiliary adcs can be independently routed to any of t he signal input pins under control of the auxadc and tx mod mode regi ster, $a7. conversions will be performed as long as a valid input source is selected; to stop the a dc, the input source should be set to ?none?. register $c0:b6, bias, must be enabled for auxiliary adc operation. averaging can be applied to the adc readings by select ing the relevant bits in the auxadc and tx mod mode register, $a7, the length of the averaging is determined by the va lue in the program blocks p3.0 and p3.1, and defaults to a value of 0. this is a rolling average system such that a proportion of the current data will be added to the last value. the pr oportion is determined by the value of the average counter in p3.0 and p3.1. for an average value of 0; 50% of the current value will be applied, for a value of 1 = 25%, 2 = 12.5% etc. the maximum useful val ue of this field is 8. averaging will begin with the current value of the auxadc, t herefore it is recommended that the auxadc be enabled for at least one sample (250s) before starting the average process to ensure that its initial value is as expected, otherwise the initial value will default to zero. high and low thresholds may be independently applied to both adc channels (the comparison is applied after averaging, if this is enabled) and an irq generated when either the high threshold is crossed by a rising edge signal or the low threshold is passed by a falling edge signal, which allows the user to implement a selectable degree of hysterisis. the th resholds are programmed via the auxadc threshold register, $b5. auxiliary adc data is read back in the auxadc data r egister ($a9) and includes the threshold status as well as the actual conversion data (subject to averaging, if enabled). see: o auxadc and tx mod mode ? $a7 write o auxadc1 data ? $a9 read o auxadc2 data ? $aa read o auxadc threshold data ? $b5 write
marine vhf audio and signalling processor CMX885 ? cml microsystems plc 30 2010 d/885/3 7.10 auxiliary dac/ramdac operation the four auxiliary dac channels are programmed vi a the auxdac control register, $a8. auxdac channel 1 may also be programmed to operate as a ramdac which will automatically output a pre- programmed profile at a programmed rate. the auxdac control register, $a8, with b12 set, controls this mode of operation. the default profile is a raised cosine (see table 7), but this may be over-written with a user defined profile by writing to program block p3.11. the ramdac operation is only available in tx mode and, to avoid glitches in the ramp profile, it is important not to change to idle or rx mode whilst the ramdac is still ramping. the auxdac outputs (avail able on their respective dac pins) hold the user- programmed level during a powersave operation if left enabled, otherwise they will return to zero. note that access to all four auxdacs is controlled by the auxdac control register, $a8, and therefore to update all auxdacs requires four writes to this regist er. it is not possible to simultaneously update all four auxdacs. see: o auxdac control/data ? $a8 write
marine vhf audio and signalling processor CMX885 7.11 digital system clock generator ref clk div /1 to 512 $ac b0-8 pd vco pll div /1 to 1024 $ab b0-9 lpf sysclk1 ref sysclk1 div vco op div /1 to 64 $ab b10-15 sysclk1 pre-clk $ac b11-15 sysclk1 output 384khz-20mhz 48 - 192khz (96khz typ) sysclk1 vco 24.576- 98.304mhz (49.152mhz typ) ref clk div /1 to 512 $ae b0-8 pd vco pll div /1 to 1024 $ad b0-9 lpf sysclk2 ref sysclk2 div vco op div /1 to 64 $ad b10-15 sysclk2 pre-clk $ae b11-15 sysclk2 output 384khz-20mhz 48 - 192khz (96khz typ) sysclk2 vco 24.576- 98.304mhz (49.152mhz typ) ref clk div /1 to 512 p3.4 pd vco pll div /1 to 1024 p3.5 lpf mainclk ref mainclk div vco op div /1 to 64 p3.3 b12-7 p3.6 b12-7 mainclk pre-clk mainclk output 384khz-50mhz (24.576mhz typ) 48 - 192khz (96khz typ) mainclk vco 24.576- 98.304mhz (49.152mhz typ) to internal adc / dac dividers auxadc div p3.3 b6-0 p3.6 b6-0 aux_adc (83.3khz typ) osc 3.0 - 12.288mhz xtal or 3.0 - 24.576mhz clock to rf synthesiser ref clk selection figure 13 digital clock generation schemes the CMX885 includes a 2-pin crystal oscillator circuit. this can either be configured as an oscillator, as shown in section 5 , or the xtal input can be driven by an exte rnally generated clock. the crystal (xtal) source frequency can go up to 12.288mhz (clock sour ce frequency up to 24.576mhz), but by default, a 3.6864mhz xtal is assumed for the f unctionality provided in the CMX885. 7.11.1 main clock operation a pll is used to create the main clock (mainclk - nom inally 24.576mhz) for the in ternal sections of the CMX885. at the same time, other internal clocks are generated by division of ei ther the xtal reference clock or the main clock. these internal clocks ar e used for determining the sample rates and conversion times of a-to-d and d-to-a converters, running a gener al purpose timer, the signal processing block. in particular, it should be noted that in idle mode the se tting of the gp timer divider directly affects the c- bus latency (with the default va lues this is nominally 250 s). cml microsystems plc 31 2010 d/885/3
marine vhf audio and signalling processor CMX885 ? cml microsystems plc 32 2010 d/885/3 the CMX885 defaults to the settings appropriate for a 3.6864mhz xtal, however if other frequencies are to be used (to facilitate commonality of xtals bet ween external rf synthesizers and the CMX885 for instance) then the program block registers p3.2 to p3.7 will need to be programmed appropriately at power-on. a table of common values is provided in table 2. see: o program block 3 ? auxdac, ramdac and clock control 7.11.2 system clock operation two system clock outputs, sysclk 1 and sysclk2, are available to drive additional circuits, as required. these are phase locked loop (pll) clocks that can be programmed via the system clock registers with suitable values chosen by the user . the system clock pll configure registers ($ab and $ad) control the values of the vco output divider and main divide registers, while the system clock ref. configure registers ($ac and $ae) control the va lues of the reference divider and signal routing configurations. the plls are designed for a reference frequency of 96khz. if not required, these clocks can be independently powersaved. the clock generation scheme is shown in the block diagram of figure 13 . note that at power-on, these outputs are disabled. see: o sysclk1 and sysclk2 pll data ? $ab, $ad write o sysclk1 and sysclk2 ref ? $ac and $ae write 7.12 gpio two pins are provided for control of external har dware. rxena and txena are driven by the device to follow the state of the rx and tx mode bits in the mode register, $c1: $c1 mode: b1 b0 txena rxena idle 0 0 1 1 rx 0 1 1 0 tx 1 0 0 1 reserved 1 1 1 1 7.13 signal level optimisation the internal signal processing of the CMX885 w ill operate with wide dynamic range and low distortion only if the signal level at all stages in the signal pr ocessing chain is kept within the recommended limits. for a device working from a 3.3v 10% supply, the maximum signal level which can be accommodated without distortion is [(3.3 x 90%) ? (2 x 0.3v)] volts pk-pk = 838mvrms, assuming a sine wave signal. compared to the reference level of 308mvrms, this is a signal of +8.69db. this level should not be exceeded at any stage. 7.13.1 transmit path levels for the maximum signal out of the mod1 and mod2 a ttenuators, the signal leve l at the output of the analogue routing block should not exceed +8.69db, assuming both fi ne and coarse output attenuators are set to a gain of 0db. this means that the out put from the soft limiter must not exceed 838mvrms. if pre-emphasis is used, an output signal at 3000hz w ill have three times the amplitude of a signal at 1000hz, so the signal level before pre-emphasis should not exceed 279mvrms. the fine input gain adjustment has a maximum attenuation of 3.5db and no gain, whereas the coarse input gain adjustment has a variable gain of up to +22.4db and no attenuati on. if the highest gain setting were used, then the maximum allowable input signal level at the micfb pin would be 54mvrms. with the lowest gain setting (0db), the maximum allowable input signal level at the micfb pin would be 718mvrms. 7.13.2 receive path levels for the maximum signal out of t he audio attenuator, the signal leve l at the output of the analogue routing block should not exceed +8.69db, assuming bot h fine and coarse output attenuators are set to a gain of 0db. that is a signal level of 838mvrms. if de-emphasis is used, an output signal at 300hz will have three and one third times the amplitude of a signal at 1000hz, so the signal level before de-
marine vhf audio and signalling processor CMX885 emphasis should not exceed 251mvrms. the fine input gain adjustment has a maximum attenuation of 3.5db and no gain, whereas the coarse input gain adjustment has a variable gain of up to +22.4db and no attenuation. if the highest gain setting were used, then the maximum allowable input signal level at the discfb pin would be 12.0mvrms. with the lowest gain setting (0db), the maximum allowable input signal level at the discfb pin would be 158mvrms . the signal level of +8.69db (838mvrms) is an absolute maximum, which should not be exceeded anyw here in the signal processing chain if severe distortion is to be avoided. in-band tones, audio tones and dsc/atis modem voice processing mux $b1: b5-2 mux $c1: b15-2 mux $a7: b15-12 $c1: b15-2 mux $b1: b9-6 audio out mod1 mod2 disc alt mic input1 input2 output1 output2 fine gain: $cd:110x fine gain: $cd:110x coarse gain: $b0:b14-12 coarse gain: $b0:b3-0 fine gain: p4.2 or $cd:011x offset: p4.4 fine gain: p4.3 or $cd:100x offset: p4.5 tone level: $cd:001x or p1.0 rx voice level: $cd:010x coarse gain: $b0:b10-8 fine gain: p4.0 fine gain: p4.1 input2 gain: $b1:b15-13 input1 gain: $b1:b12-10 note: rx voice level adjust ($cd:010x) is only active in rx mode tx mult ($cd:101x) is only active in tx mode tx mult x2,x4,x8: $cd:101x figure 14 level adjustments 7.14 c-bus interface 7.14.1 interrupt operation the CMX885 will issue an interrupt on the irqn line when the irq bit (bit 15) of the status register and the irq mask bit (bit 15) are both set to 1. the irq bit is set when the state of the interrupt flag bits in the status register change from a 0 to 1 and the corres ponding mask bit(s) in the interrupt mask register is(are) set. enabling an interrupt by setting a mask bit (0 1) after the corresponding status register bit has already been set to 1 will also cause the irq bit to be set. all interrupt flag bits in the status register, exc ept the prg flag (bit 0), are cleared and the interrupt request is cleared following the command/address phase of a c-bus read of the status register. the prg flag bit is set to 1 only when it is permissible to write a new word to the programming register. see: o status ? $c6 read o interrupt mask ? $ce 7.14.2 general notes in normal operation, the most significant registers are: o mode control ? $c1 write o status ? $c6 read o analogue output gain ? $b0 write o input gain and output signal routing ? $b1 write o audio control ? $c2 write setting the mode control register to either rx or tx will automatically increase the internal clock speed to its operational rate, whilst setting the mode control regist er to idle will automatically return the internal clock to a lower (powersaving) rate. to access the program blocks (through the programming register, $c8) the device must be in idle mode. under normal circumstances, the CMX885 manages the main clock control automatically, using the default values loaded in program block 3. ? cml microsystems plc 33 2010 d/885/3
marine vhf audio and signalling processor CMX885 ? cml microsystems plc 34 2010 d/885/3 8 configuration guide 8.1 c-bus register summary addr. (hex) register word size (bits) $01 w c-bus reset 0 $a7 w auxadc and tx mod mode 16 $a8 w auxdac control/data 16 $a9 r auxadc1 data 16 $aa r auxadc2 data 16 $ab w sysclk1 pll data 16 $ac w sysclk1 ref 16 $ad w sysclk2 pll data 16 $ae w sysclk2 ref 16 $af reserved $b0 w analogue output gain 16 $b1 w input gain and output signal routing 16 $b2 reserved $b3 reserved $b4 reserved $b5 w auxadc threshold data 16 $b6 reserved $b7 reserved $b8 reserved $b9 reserved $ba reserved $bb r nwr status and data 16 $bc reserved $bd reserved $be reserved $bf reserved $c0 w power-down control 16 $c1 w mode control 16 $c2 w audio control 16 $c3 w tx inband tones 16 $c4 reserved $c5 r rx data 1 16 $c6 r status 16 $c7 w modem configuration 16 $c8 w programming 16 $c9 reserved $ca w tx data 1 16 $cb reserved $cc r tone status / device ident code 16 $cd w audio tone 16 $ce w interrupt mask 16 $cf reserved the detailed descriptions of the c-bus registers ar e presented in numerical order and should be read in conjunction with the relevant functi onal descriptions in the datasheet.
marine vhf audio and signalling processor CMX885 ? cml microsystems plc 35 2010 d/885/3 all other c-bus addresses (including those not list ed above) are either reserved for future use or allocated for production testing and must not be accessed in normal operation. 8.1.1 reset operations a reset is automatically performed when power is app lied to the CMX885. a reset can be issued as a c-bus command, either as a general reset command ( $01), or by setting the appropriate bit (b5) in the powerdown control register ($c0). in the latter case , an option exists to protect the values held in the program block (which is accessed via the programming register, $c8). the action of each reset type is shown in the table below: table 4 reset operations reset type protect bit ($c0 b4) state program block state 1 power on cleared by h/w default 2 general reset (c-bus $01) cleared by h/w default 3 reset (c-bus $c0 b5) 0 default 4 reset (c-bus $c0 b5) 1 protected 8.1.2 general reset ? $01 write the general reset command has no data attached to i t. it sets all operational c-bus registers to $0000, (apart from the registers marked as reserved ). note that some transient data may appear in the following registers during the reset and power-up processes ? this should be ignored: aux adc 1 data $a9 aux adc 2 data $aa nwr status and data $bb rx data 1 $c5 status $c6 tone status / ident $cc
marine vhf audio and signalling processor CMX885 ? cml microsystems plc 36 2010 d/885/3 8.1.3 auxadc and tx mod mode ? $a7 write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 tx mod mode aux adc2 av mode aux adc2 i/p select aux adc1 av mode aux adc1 i/p select 0 0 tx mod mode b15 b14 b13 b12 output1 output2 0 0 1 1 inband inband 0 0 1 0 inband bias 0 0 0 1 inband bias 0 0 0 0 bias bias to select the routing between the output1, output2 and mod1, mod2 and audio, see section 8.1.10 auxadc averaging mode b11 b10 auxadc2 b6 b5 auxadc1 1 1 reserved 1 0 reserved 0 1 rolling average, uses program block 3.0/3.1 value 0 0 no averaging auxadc input select b9 b8 b7 auxadc2 b4 b3 b2 auxadc1 1 1 1 adc4 1 1 0 adc3 1 0 1 adc2 1 0 0 adc1 0 1 1 micn 0 1 0 altn 0 0 1 discn 0 0 0 off
marine vhf audio and signalling processor CMX885 ? cml microsystems plc 37 2010 d/885/3 8.1.4 auxdac control/data ? $a8 write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ena 0 0 ram dac dac sel aux dac data/ramdac control b15 enable selected aux dac 0 = disable 1 = enable b14 reserved b13 reserved b12 ramdac enable 0 = auxdac1 operates normally 1 = auxdac1 operates as a ramdac 4 . data in b0-6 controls the ramdac functions. b11-b10 select the auxdac that b9-b0 data will be written to 00 = auxdac1 01 = auxdac2 10 = auxdac3 11 = auxdac4 b9-b0 auxdac data (unsigned) note: the c-bus latency period (250s) should be observed between successive writes to this register. note: when $a8 b12 is set to 1, writing data to this register controls the ramdac settings. writing to auxdac1 whilst the ramdac is still ramping ma y cause un-intended operation. in this mode b10 and b11 are ignored and b9 to b0 perform the following functions: b9 reserved , clear to 0 b8 reserved , clear to 0 b7 reserved , clear to 0 b6 ramdac ram access, 0 resets the internal ramdac address pointer ramdac scan time b5 b4 b3 divider time (ms) 0 0 0 1024 10.50 0 0 1 512 5.25 0 1 0 256 2.63 0 1 1 128 1.31 1 0 0 64 0.66 1 0 1 32 0.33 1 1 0 16 0.16 1 1 1 8 0.08 b2 scan direction: 0 = ramp down 1 = ramp up b1 autocycle 0 = disable 1 = continuous ramp up/down b0 ramdac start 0 = stop 1 = start ramdac ramping to initiate a ramdac ramp up write: $9005 to initiate a ramdac ramp down, write: $9001 note that initiating a ramdac scan will automatic ally bring auxdac1 out of powersave. to place auxdac1 back into powersave, it must be written to explicitly. do not change idle/rx/tx mode whilst the ramdac is still ramping. 4 do not write to directly to auxdac1 whilst the ramdac is in operation. ramdac is only available when in tx mode.
marine vhf audio and signalling processor CMX885 ? cml microsystems plc 38 2010 d/885/3 8.1.5 auxadc1 data ? $a9 read 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 threshold status x x x x aux adc 1 data b15-14 threshold status b15 = 1 signal is above the high threshold = 0 signal is below the high threshold b14 = 1 signal is below the low threshold = 0 signal is above the low threshold b13 reserved b12 reserved b11 reserved b10 reserved b9?0 auxadc1 data or last reading (unsigned) 8.1.6 auxadc2 data ? $aa read 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 threshold status x x x x aux adc 2 data b15-14 threshold status b15 = 1 signal is above the high threshold = 0 signal is below the high threshold b14 = 1 signal is below the low threshold = 0 signal is above the low threshold b13 reserved b12 reserved b11 reserved b10 reserved b9-0 auxadc2 data or last reading (unsigned)
marine vhf audio and signalling processor CMX885 ? cml microsystems plc 39 2010 d/885/3 8.1.7 sysclk1 and sysclk2 pll data ? $ab, $ad write c-bus address: $ab ? sysclk1 pll c-bus address: $ad ? sysclk2 pll 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 vco op divide ratio <5-0> pll feedback divide ratio <9-0> b15-10 divide the selected output clock source by the value in these bits, to generate the system clock output. divide by 64 is selected by setting these bits to 0. b9-0 divide system clock pll vco clock by val ue set in these bits as feedback to the pll phase detector (pd); when the pll is stable, this will be the same frequency as the internal reference as set by b8-b0 of the system clock reference and source configuration register ($ac). divide by 1024 is selected by setting these bits to 0. 8.1.8 sysclk1 and sysclk2 ref ? $ac and $ae write c-bus address: $ac ? sysclk1 ref c-bus address: $ae ? sysclk2 ref 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 select & ps clock sources o/p sl ew ref clock divide ratio <8-0> b15,12,11 clock output divider source sysclk1 source b15 b12 b11 xtal 0 x x sysclk1 pll 1 0 0 main pll 1 0 1 test 1 1 x sysclk2 source b15 b12 b11 xtal 0 x x sysckl2 pll 1 0 0 main pll 1 0 1 sysclk1 pll 1 1 0 test 1 1 1 b14 powersave pll 0 = powersave 1 = enabled b13 powersave output divider 0 = powersave / bypass 1 = enabled b10-9 output slew rate b10 b9 output slew rate 0 0 normal 0 1 slow 1 0 fast 1 1 fast b8-b0 reference clk divide value. divide by 512 func tion is selected by setting these bits to 0. note that after a general reset, there will be no signal present on the sysclk1 and sysclk2 pins.
marine vhf audio and signalling processor CMX885 ? cml microsystems plc 40 2010 d/885/3 8.1.9 analogue output gain ? $b0 write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 inv_1 mod1 attenuation inv_2 mod2 attenuation ramp up/dn 0 0 0 audio output attenuation b15 output1 polarity 0 = true 1 = inverted b11 output2 polarity 0 = true 1 = inverted used when interfacing with rf. any change will take place immediately (within the c-bus latency period) after these bits are changed. b14 b13 b12 mod1 output attenuation b10 b9 b8 mod2 output attenuation 0 0 0 >40db (default) 0 0 1 12db 0 1 0 10db 0 1 1 8db 1 0 0 6db 1 0 1 4db 1 1 0 2db 1 1 1 0db b7 ramp up/down enable 0 = off 1 = on when bit 7 is set to 1 the mod output signal s are ramped to reduce transients in the transmitted signal. the ramp up/down time is se t in the ?ramp rate control? section of the programming register (p4.6). bits 6 to 4 are reserved - set to 0. b3 b2 b1 b0 audio output attenuation 0 0 0 0 >60db (default) 0 0 0 1 44.8db 0 0 1 0 41.6db 0 0 1 1 38.4db 0 1 0 0 35.2db 0 1 0 1 32.0db 0 1 1 0 28.8db 0 1 1 1 25.6db 1 0 0 0 22.4db 1 0 0 1 19.2db 1 0 1 0 16.0db 1 0 1 1 12.8db 1 1 0 0 9.6db 1 1 0 1 6.4db 1 1 1 0 3.2db 1 1 1 1 0db note that fine level control of output 1 and output 2 can be achieved with the fine output gain 1 and fine output gain 2 registers (p4.2-3). these affect the mod1 , mod2 and audio outputs according to the routing set in registers $a7 and $b1.
marine vhf audio and signalling processor CMX885 ? cml microsystems plc 41 2010 d/885/3 8.1.10 input gain and output signal routing ? $b1 write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 input 2 gain input 1 gain mod1 source mod2 source audio source input 1 routing input 2 routing 0 0 b12 b11 b10 input 1 gain b15 b14 b13 input 2 gain 0 0 0 0db (default) 0 0 1 3.2db b7 mod2 source 0 1 0 6.4db 0 bias -> mod2 (default) 0 1 1 9.6db 1 output 2 -> mod2 1 0 0 12.8db 1 0 1 16.0db b6 audio source 1 1 0 19.2db 0 bias -> audio (default) 1 1 1 22.4db 1 output 1 -> audio b9 b8 mod1 source 0 0 bias (default) 0 1 bias 1 0 output 1 -> mod1 1 1 output 2 -> mod1 b5 b4 input 1 signal routing b3 b2 input 2 signal routing 0 0 bias (default) 0 1 discn 1 0 altn 1 1 micn output 1 and output 2 signal sour ces are also defined in section 8.1.3 . bits 1, 0 are reserved ? clear to 0. there are a number of applications where it may be desirable to split the processing across both inputs, such as monitoring two rf receivers, in which case , input 1 could be routed fr om the discn input with voice and dsc or nwr processing set to input 2 from the altn input. similarly, for the output routing, under normal operati on, in tx mode, output 1 would be routed to mod1 and output 2 to mod2. the signals that appear on ou tput 1 and output 2 are defined in the tx mod mode register, $a7:b14 to b12. if the audio output is selected in tx mode (using b6) it will present the signal that has been routed to output 1. this can be used for ?sidetone? when tr ansmitting inband signalling in 1 or 2-point modulation modes. in rx mode, the audio process is automatically routed to output 1. an audio output is only available when in rx or tx mode. 8.1.11 reserved ? $b2 write 8.1.12 reserved ? $b3 write 8.1.13 reserved ? $b4 8-bit read
marine vhf audio and signalling processor CMX885 ? cml microsystems plc 42 2010 d/885/3 8.1.14 auxadc threshold data ? $b5 write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 adc sel high /low 0 0 0 0 aux adc threshold data b15 auxadc select 0 = auxadc1 1 = reserved b14 high/low select 0 = low threshold 1 = high threshold b13 reserved 0 b12 reserved 0 b11 reserved 0 b10 reserved 0 b9-0 threshold data 8.1.15 reserved ? $b6 write 8.1.16 nwr status and data ? $bb read 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 nwr status x x x x nwr same data b15 nwr wat tone status 0 = no tone 1 = wat tone detected b14 nwr same data terminator 0 = no dat a 1 = data terminator nnnn detected b13 nwr same data header 0 = no data 1 = data header zczc detected b12 nwr same data status 0 = no data 1 = data available b11 reserved b10 reserved b9 reserved b8 reserved b7?0 nwr same data 8.1.17 powerdown control ? $c0 write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 alt amp mic amp disc amp ip1 ena op1 ena op2 ena mod1 ena mod2 ena audio ena bias reset protect xtal dis ip2 ena 0 0 b15 alt amp enable 0 = off 1 = enabled b14 mic amp enable 0 = off 1 = enabled b13 disc amp enable 0 = off 1 = enabled b12 input 1 enable 0 = off 1 = enabled b11 output 1 enable 0 = off 1 = enabled b10 output 2 enable 0 = off 1 = enabled b9 mod1 enable 0 = off 1 = enabled b8 mod2 enable 0 = off 1 = enabled b7 audio enable 0 = off 1 = enabled b6 bias block enable 0 = off 1 = enabled b5 reset 0 = normal 1 = reset/powersave b4 program block protect 0 = normal 1 = protected if cleared, the program blocks will be initialised on power on or reset. if set, then the program blocks will retain their previous contents. b3 xtal disable 0 = enabled 1 = disabled / powersave setting this bit effectively stops all signal processing within the device. b2 input 2 enable 0 = off 1 = enabled b1 reserved 0 1 = do not use b0 reserved 0 1 = do not use note: care should be taken when writing to b5 and b3. these are automatically programmed to an operational state following a power-on (ie: all 0s). writi ng a 1 to either b5 or b3 will effectively cause the
marine vhf audio and signalling processor CMX885 ? cml microsystems plc 43 2010 d/885/3 device to cease all processing activity, including responding to other c-bus commands (except general reset, $01). when b5 is set, the device will be held in reset and all signal processing will cease (including auxadc operation. when b3 is set the xtal is disabled. when b3 is subsequently cleared, it may take some time for the clock signal to become stable, hence care shoul d be taken in using this feature. 8.1.18 mode control ? $c1 write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 audio nwr inband modes 0 0 0 data mode idle/rx/tx b15 reserved 0 b14 audio enable 0 = off 1 = enabled (uses input 1 source) b13 nwr source 0 = input 1 1 = input 2 b12 nwr enable 0 = off 1 = enabled (enables both wat and same) b11 inband source 0 = input 1 1 = input 2 b10 audio generator enable 0 = off 1 = enabled b9 reserved 0 b8 dtmf enable 0 = off 1 = enabled b7 reserved 0 b6 reserved 0 b5 reserved 0 b4 modem source 0 = input 1 1 = input 2 b3 reserved 0 b2 modem enable 0 = off 1 = enabled b1-0 operational mode 00 idle 01 rx 10 tx 11 reserved changes to the settings of the bits in this register are implemented as soon as t hey are received over the c-bus (note that the c-bus has a potential latency of up to 250 s). in tx mode, it is not permissible to set both b3 and b2 at the same time. in tx mode, it is only permissible to select one of the following at any time: audio inband signalling dsc signalling note that if the audio processing bit (b14) is set at the same time as an inband signalling bit in tx mode, the inband signal will be subjected to a 6db gain. it is essential that changes to the programming regi ster and the audio control register are completed before entering rx or tx mode.
marine vhf audio and signalling processor CMX885 ? cml microsystems plc 44 2010 d/885/3 the following other registers or bits can be changed as appropriate (note: not all possible changes are appropriate), whilst the device is in tx or rx mode: ? analogue output gain register ($b0) ? auxadc and tx mod mode register ($a7) ? input gain and signal routing register ($b1) ? power down control register ($c0) ? tx inband tones register ($c3) ? tx data registers ($ca & $cb) ? audio tone register ($cd) ? interrupt mask register ($ce) 8.1.19 audio control ? $c2 write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 scra- mble 0 emph 12k5 25k hpf 0 0 0 0 0 0 0 0 0 0 b15 audio scrambling enable 0 = off 1 = enabled b14 reserved b13 audio pre/de-emphasis 0 = off 1 = enabled 5 b12 audio 12.5khz filter enable 0 = off 1 = enabled b11 audio 25khz filter enable 0 = off 1 = enabled b10 audio 300hz hpf enable 0 = off 1 = enabled b9-0 reserved 8.1.20 tx inband tones ? $c3 write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 twist sgl tx dtmf tone b15-6 reserved, clear to 0. b5 dtmf twist 0 = normal 1 = -2db of twist applied to the lower dtmf tone. b4 dtmf single tone 0 = normal 1 = single tone, see table 3 dtmf tone pairs b3-0 dtmf tone value ? see table 3 dtmf tone pairs see section 8.1.21. 8.1.21 rx data 1 ? $c5 read bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 $c5 flag dsc character 0 flag dsc character 1 this word holds the most recent bytes (byte 0 and 1) of dsc data decoded. re ceived data is continuous, if the data is not read before the next data is received the current dat a will be over-written. in dsc formatted mode, if the flag bit (b15 or b7) is set, then the accompanying character has been received with an error detected. 5 in order to pre-emphasise the fsk data, program block p0.0 bit 11 should be set.
marine vhf audio and signalling processor CMX885 ? cml microsystems plc 45 2010 d/885/3 8.1.22 status ? $c6 read 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 irq nwr res dtmf res res aux adc2 aux adc1 data end data rdy res res dsc res res prg b15 irq changes in the status register will cause this bit to be set to 1 if the corresponding interrupt mask bit is enabled. an interrupt request is iss ued on the irqn pin when this bit is 1 and the irq mask bit (b15 of interrupt mask register, $ce) is set to 1. b14 nwr status change the noaa weather receiver has detected a c hange in the status of the wat tone or same data. the nwr data/status register $bb s hould be read to determine the exact cause. b13 reserved b12 dtmf event a valid dtmf tone has been detected and can be r ead from the tone status register, $cc. b11 reserved b10 reserved b9 auxadc2 threshold change aux adc2 signal has just gone above the high threshold or has just gone below the low threshold. the auxadc2 data register $aa should be read to determine the exact cause. b8 auxadc1 threshold change aux adc1 signal has just gone above the high threshold or has just gone below the low threshold the auxadc1 data register $a9 should be read to determine the exact cause. b7 data end rx mode: this bit is not used, so its value should be ignored. see section 7.7.1 . tx mode: this will be set when the last bit of dsc data has been transmitted. after allowing a short time delay associated with the exter nal components and radio circuitry, the host may power down the CMX885 and transmitter or set the CMX885 to transmit or receive new information as appropriate. b6 data ready tx mode: indicates that new transmit data is required. rx mode: received data is ready to be read. for continuous transmission or reception of in formation, a data transfer should be completed within the time appropriate for that data. b5 reserved b4 reserved b3 dsc when set to 1, this bit indicates that a valid dsc data sequence has been received. b2 reserved b1 reserved b0 prg when set to 1, this bit indicates that the progr amming register, $c8 is available for the host to write to it. cleared by writing to the programming register, $c8 bits 2 to 15 of the status register are cleared to 0 after the status register is read. the data in this register is not valid if bit 5 of the power down control register, $c0 is set to 1.
marine vhf audio and signalling processor CMX885 ? cml microsystems plc 46 2010 d/885/3 8.1.23 modem configuration ? $c7 write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 sync synd synt en nwr data en dsc en raw last tx data 0 0 0 0 0 0 user bit 0 0 this register configures the way the CMX885 handles dsc data in tx and rx modes. b15 sync detect 0 = off 1 = enabled b14 synd detect 0 = off 1 = enabled b13 synt detect 0 = off 1 = enabled note: sync, synd and synt patterns are defined in program blocks p0.0-3 b12 en_nwr_data 0 = disabled 1 = enabled the en_nwr_data bit is required to disable the nwr same data decoder at the end of a data frame. the decoder will detect and respond to the a rrival of a sync signal (if $c1:b12 is set to 1), and report any following data, however t he host will need to decode the data from the CMX885, recognise the end of data and then disable the same decoder through this bit. setting this bit to 1 will disable the sy nc search and output data immediately. b11 en_dsc data mode 0 = disabled 1 = enabled setting this bit selects dsc modem operation. the modem enable bit $c1:b2 will start/stop the modem. b10 en_raw: 0 = data packetising on 1 = raw data mode this bit selects the raw or formatt ed (data packetising) mode for dsc data. dsc receive mode: b10 = 1: device will look for the programmed fram e sync. pattern, raise an interrupt (if enabled) and decode the following data 16 bits at a time, maki ng them available in rx data 1 register ($c5). dsc transmit mode: b10 = 1: device will transmit data 16 bits at a time from tx data 1 register ($ca). bit and frame sync pattern generation and all formatting of the data have to be performed by the host in this case. b9 last tx data: this is only valid when transmitting data in dsc formatted mode and indicates to the CMX885 that it can cease modulation. the host must set this bit to 1 immediately after the interrupt for ?load more data? occurs $c6:b6. in receive, or when transmitting other message formats, this bit must be cleared to 0. b8-3 reserved, clear to 0 b2 user bit. may be freely used by the host in dsc modes. this bit has no effect on the message format or encoding and will be reported in the rx data 1 r egister for the receiving host to use as appropriate. this bit could be used to indicate a special message, e.g. one containing handset or channel set-up information. b1-0 reserved, clear to 0 8.1.24 programming register ? $c8 write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 program block address program block data see section 8.2 for a definition of program block operation. 8.1.25 tx data 1 ? $ca write bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 $ca flag dsc character 0 flag dsc character 1
marine vhf audio and signalling processor CMX885 ? cml microsystems plc 47 2010 d/885/3 this word holds the next 2 bytes (byte 0 and 1) of dsc data to be transmitted. outgoing data is continuous, if new data is not pr ovided before the current data has been transmitted the current data will be re-transmitted, until new data is provided. transmission of curr ent data will be completed before transmission of newly loaded data begins. see section 7.7.2 . in dsc formatted mode, if the flag bit (b15 or b7) is set, then the accompanying character is ignored. 8.1.26 tone status ? $cc read 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 device ident code x dtmf tone detected dt x x x x x x x x x x after power-on or general reset, this register will cont ain the device ident code related to this particular device. the host c may use this to confirm that the device is in its correct operational mode before attempting to actively use the device. in normal operation, this word holds the current stat us of the CMX885 dtmf detector. this word should be read by the host after an interrupt caused by a dtmf event. in tx mode this register will be cleared to 0. b15 reserved ? ignore this bit. b10 set if b14-11 represent dtmf tone. b14-11 detected inband frequency; identifie s the frequency by its position in table 3 dtmf tone pairs . a change in the state of bits 14 to 10 will cause the status register $c6:b12, to be set to 1. b9-0 reserved ? ignore these bits.
marine vhf audio and signalling processor CMX885 ? cml microsystems plc 48 2010 d/885/3 8.1.27 audio tone ? $cd write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 audio tone frequency 0 0 1 0 audio tone level 0 1 0 0 rx voice level 0 1 1 0 output1 fine gain (also see p4.2) 1 0 0 0 output2 fine gain (also see p4.3) 1 0 1 0 tx voice level multiplier 1 0 1 1 reserved 1 1 0 0 mod1 and mod2 fine attenuation 1 1 0 1 reserved 1 1 1 0 reserved 1 1 1 1 reserved all other values reserved bits 15-12 determine how the remaining bit fields will be interpreted: 0000 2 : when the appropriate bit of the mode control regist er $c1:b10 is set, an audio tone will be generated with the frequency set by bits (11-0) of the audio tone regi ster in accordance with the formula below. if bits 11-0 are programmed with 0, no tone (i.e. v bias ) will be generated when the audio tone is enabled. frequency = audio tone (i.e. 1hz per lsb) the audio tone frequency should only be set to generate frequencies from 288hz to 3000hz. the host should disable other audio band signalling and set the correct audio routing before generating an audio tone and re-enable signalling and audio routing on completion of the audio tone. the timing of intervals between these actions is controlled by the host c. this register may be written to whilst the audio tone is being generated, any change in frequency will take place after the end of the c-bus write to this register . this allows complex s equences (e.g. ring or alert tunes) to be generated for the local speaker (tx or rx via the audio pin) or transmitted signal (tx via the mod1/mod2 pins). 0010 2 : the audio tone level may be attenuated by the value written to b11-0. the default value of $fff is equivalent to x1. note that this adjustment w ill affect all signals generated by the in-band signalling block (dtmf, fsk, audio tone). this register operates in parallel with p1.0, but allows the level to be adjusted ?on-the-fly? without needing to drop back into idle mode. 0100 2 : in rx mode, the voice level may be attenuated by the value written to b11-0. the default value of $fff is equivalent to x1. note that this adjustment will onl y affect signals in the voice processing path as enabled by the mode control register $c1:b14. this allows the voice level to be adjusted ?on-the-fly? and in conjunction with the audio output attenuator $b0:b3 to b0, offers a ?fine gain? volume control. approximate values for 0.2db steps are shown in table 5.
marine vhf audio and signalling processor CMX885 ? cml microsystems plc 49 2010 d/885/3 b11-0 value (hex) attenuation (db) b11-0 value (hex) attenuation (db) fff 0 d50 1.6 f90 0.2 cf0 1.8 f40 0.4 cb0 2.0 ee0 0.6 c60 2.2 ea0 0.8 c20 2.4 e50 1.0 bf0 2.6 de0 1.2 ba0 2.8 da0 1.4 b60 3.0 table 5 voice level attenuation 0110 2 : the output 1 level may be attenuated by the value written to b11-0. the default value of $fff is equivalent to x1. this register operates in parallel with p4.2, but allows the level to be adjusted ?on-the-fly? without needing to drop back into idle mode. 1000 2 : the output 2 level may be attenuated by the value written to b11-0. the default value of $fff is equivalent to x1. this register operates in parallel with p4.4, but allows the level to be adjusted ?on-the-fly? without needing to drop back into idle mode. 1010 2 : this sets the value of the tx voice level multiplier at the output of the tx limiter stage. this can be useful in situations where it has been necessary to use a small limiting threshold and still maintain an acceptable level at the mod outputs. the default state is x1. b2 b1 b0 tx voice level multiplier 0 0 0 x1 0 0 1 x2 0 1 0 x4 0 1 1 x8 1 0 0 x16 1 0 1 x32 1100 2 : mod1 and mod2 fine attenuator controls. in conjunction with the coarse attenuator register ($b0), these bits allow fine control over the mod1 and mod2 leve ls in 0.2db steps. additional gain and offset control of output 1 and output 2 is also provided in register $cd:0111 and $cd:1000 settings as well as program blocks p4.2 ? 4.5. these bits may be changed whilst the device is in tx or rx modes. b3 b2 b1 b0 mod1 fine output attenuation b7 b6 b5 b4 mod2 fine output attenuation 0 0 0 0 0db 0 0 0 1 0.2db 0 0 1 0 0.4db 0 0 1 1 0.6db 0 1 0 0 0.8db 0 1 0 1 1.0db 0 1 1 0 1.2db 0 1 1 1 1.4db 1 0 0 0 1.6db 1 0 0 1 1.8db
marine vhf audio and signalling processor CMX885 ? cml microsystems plc 50 2010 d/885/3 8.1.28 interrupt mask ? $ce write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 irq nwr 0 dtmf 0 0 aux adc2 aux adc1 data end data rdy 0 0 dsc 0 0 prg bit value function 15 1 enable selected interrupts 0 disable all interrupts (irqn pin not activated) 14 1 enable nwr detection 0 disabled 13 0 reserved 12 1 enable interrupt when a valid dtmf tone is detected 0 disabled 11 0 reserved 10 0 reserved 9 1 enable interrupt when the aux adc 2 status bit changes 0 disabled 8 1 enable interrupt when the aux adc 1 status bit changes 0 disabled 7 1 enable interrupt when dsc data transmission has ended 0 disabled 6 1 enable interrupt when a dsc data transfer is required 0 disabled 5 0 reserved 4 0 reserved 3 1 enable interrupt when valid dsc data is detected 0 disabled 2 0 reserved 1 0 reserved 0 1 enable interrupt when prog flag bit of t he status register changes from 0 to 1 (see programming register $c8) 0 disabled 8.1.29 reserved ? $cf write this c-bus address is allocated for production test ing and must not be accessed in normal operation.
marine vhf audio and signalling processor CMX885 ? cml microsystems plc 51 2010 d/885/3 8.2 programming register operation in order to support radio systems that may not comply with the default settings of the CMX885 , a set of program blocks is available to customise the features of the device. it is env isaged that these blocks will usually only be written to following a power-on of the device and hence can only be accessed while the device is in idle mode. access to these bl ocks is via the programming register ($c8). all other interrupt sources should be disabled and t he auxadcs switched off while loading the program blocks. the programming register should only be written to w hen the prg flag in the status register $c8:b0 is set to 1 and the rx and tx modes are disabled (bits 0 and 1 of the mode control register both 0) and the auxadc is disabled. the prg flag is cleared when the programming register is written to by the host. when the corresponding programming action has been completed (normally wi thin the c-bus latency period, 250s) the CMX885 will set the flag back to 1 to indicate that it is now safe to write the next programming value. the programming register must not be written to while t he prg flag bit is 0. programming is performed by writing a sequence of 16-bit words to the programming regi ster in the order shown in the following tables. writing data to the programming register must be performed in the order shown for each of the blocks, however the order in which the blocks are written is not critical. if later words in a block do not require updating the user may stop programming that block when the last change has been performed. e.g. if only 'fine output atten 1' needs to be changed the host will need to write to p4.0, p4.1 and p4.2 only. the user must not exceed the def ined word counts for each block. the internal pointer for each program block write is initialised by setting bit 15 to 1. bits 14-12 are then used to select the particular program block in use as shown in table 6 table 6 program block selection . subsequent writes to the program register (with b15 cleared to 0) will increment the poi nter until the end of the program block is reached. program block 3 has an additional feature to facilit ate ramdac programming, where the first eleven entries of the block may be skipped by setting both b15 and b10 to 1 to initialise the pointer directly to the start of the ramdac table. b15 b14 b13 b12 bit field (max) 1 0 x x select block 4 14 1 1 0 0 select block 0 12 1 1 0 1 select block 1 12 1 1 1 0 select block 2 12 1 1 1 1 select block 3 12 once the final write to the programming register has been executed, a final check of the prg flag should be performed before returning to normal operation.
marine vhf audio and signalling processor CMX885 ? cml microsystems plc 52 2010 d/885/3 8.2.1 program block 0 ? modem configuration bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 p0.0 1 1 0 0 pre 0 dsc frame sync lsb p0.1 0 1 0 0 0 dsc frame sync msb p0.2 0 1 0 0 0 dsc frame synd lsb p0.3 0 1 0 0 0 dsc frame synd msb p0.4 0 1 0 0 0 reserved p0.5 0 1 0 0 0 reserved p0.6 0 1 0 0 0 reserved p0.7 0 1 0 0 0 reserved p0.8 0 1 0 0 0 dsc bit sync lsb p0.9 0 1 0 0 0 dsc bit sync msb default values: p0.0 $23 p0.5 $00 p0.1 $cb p0.6 $00 p0.2 $33 p0.7 $00 p0.3 $b4 p0.8 $55 p0.4 $00 p0.9 $55 this initiates the device with the dsc frame sync pa ttern of $cb23 and bit sync of alternate 1s and 0s. $c8 (p0.0-3) dsc frame sync bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 p0.0 1 1 0 0 pre 0 dsc frame sync lsb p0.1 0 1 0 0 0 dsc frame sync msb p0.2 0 1 0 0 0 dsc frame synd lsb p0.3 0 1 0 0 0 dsc frame synd msb bits 7 to 0 set the frame sync pattern used in tx and rx dsc data. bit 7 of the msb is compared to the earliest received data. note that synt is the inverse pattern of sync. bit 11 enables pre-emphasis on dsc transmission. $c8 (p0.4-7) reserved $c8 (p0.8-9) dsc bit sync bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 p0.8 0 1 0 0 0 dsc bit sync lsb p0.9 0 1 0 0 0 dsc bit sync msb this bit pattern is used w hen transmitting the bit sync.
marine vhf audio and signalling processor CMX885 ? cml microsystems plc 53 2010 d/885/3 8.2.2 program block 1 ? inband tone setup bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 p1.0 1 1 0 1 audio band tones/data tx level 0 default values: p1.0: $800 $c8 (p1.0) audio band tones tx level bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 p1.0 1 1 0 1 audio band tones/data tx level 0 bits 11 (msb) to 1 (lsb) set the transmitted dtmf , audio tone and fsk signal level (pk-pk) with a resolution of av dd /2048 per lsb (1.611mv per lsb at av dd =3.3v). valid range for this value is 0 to 1536 ? use with care as higher values may result in signal ?clipping?. bit 0 reserved 8.2.3 program block 2 ? reserved 8.2.4 program block 3 ? auxdac, ramdac and clock control this block is divided into two sub-blocks to facilitat e loading the ramdac buffer. set bit 15 to restart a loading sequence. if bit 10 is set then loading the first ten locations will be skipped. if bit 10 is clear, the first ten locations must be loaded befor e continuing to the ramdac load. the internal clock dividers only require modifi cation if a non-standard xtal frequency is used (see table 2 ). bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 p3.0 1 1 1 1 0 0 0 0 auxadc1 average counter p3.1 0 1 1 1 0 0 0 0 reserved p3.2 0 1 1 1 gp timer value in idle mode p3.3 0 1 1 1 vco output and aux clk divide in idle mode p3.4 0 1 1 1 ref clk divide in rx or tx mode p3.5 0 1 1 1 pll clk divide in rx or tx mode p3.6 0 1 1 1 vco output and aux clk divide in rx or tx mode p3.7 0 1 1 1 0 0 0 0 internal adc/dac clk divide in rx or tx mode p3.8 0 1 1 1 0 0 0 0 adc internal control 1 p3.9 0 1 1 1 0 0 0 0 adc internal control 2 p3.10 0 1 1 1 0 0 0 0 0 0 0 0 adc internal control 3 p3.11 1 1 1 1 0 1 user defined ramdac data 0 p3.xx 0 1 1 1 0 1 user defined ramdac data xx p3.74 0 1 1 1 0 1 user defined ramdac data 63 default values: p3.0 $000 p3.1 $000 p3.2 - p3.7: see table 2 p3.8 $000 p3.9 $101 p3.10 $002 p3.11 - p3.74: see table 7
marine vhf audio and signalling processor CMX885 table 7 ramdac values default ramdac contents after reset (hex) 0 000 1 001 2 003 3 006 4 00a 5 010 6 017 7 01f 8 028 9 033 10 03e 11 04b 12 059 13 068 14 078 15 089 16 09a 17 0ad 18 0c1 19 0d5 20 0ea 21 100 22 116 23 12d 24 145 25 15d 26 175 27 18e 28 1a7 29 1c0 30 1d9 31 1f3 32 20c 33 226 34 23f 35 258 36 271 37 28a 38 2a2 39 2ba 40 2d2 41 2e9 42 2ff 43 315 44 32a 45 33e 46 352 47 365 48 376 49 387 50 397 51 3a6 52 3b4 53 3c1 54 3cc 55 3d7 56 3e0 57 3e8 58 3ef 59 3f5 60 3f9 61 3fc 62 3fe 63 3ff 8.2.5 program block 4 ? gain and offset setup bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 p4.0 1 0 fine input gain 1 p4.1 0 0 fine input gain 2 p4.2 0 0 fine output gain 1 p4.3 0 0 fine output gain 2 p4.4 0 0 output 1 offset control p4.5 0 0 output 2 offset control p4.6 0 0 ramp rate control p4.7 0 0 limiter setting p4.8 0 0 scrambler inversion frequency p4.9 0 0 audio filter sequence p4.10 0 0 reserved p4.11 0 0 input agc threshold level default values: p4.0 $8000 p4.6 $0000 p4.1 $0000 p4.7 $3fff p4.2 $0000 p4.8 $119a p4.3 $0000 p4.9 $001b p4.4 $0000 p4.10 $0608 p4.5 $0000 p4.11 $0fff ? cml microsystems plc 54 2010 d/885/3
marine vhf audio and signalling processor CMX885 ? cml microsystems plc 55 2010 d/885/3 $c8 (p4.0) fine input gain 1 and fine input gain 2 bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 p4.0 1 0 fine input gain 1 (unsigned integer) p4.1 0 0 fine input gain 2 (unsigned integer) gain = 20 log([32768-ig]/32768)db. ig is the unsigned int eger value in the ?fine input gain? field. fine input gain adjustment should be kept within the r ange 0 to -3.5db. this adjustment occurs after the coarse input gain adjustment (register $b1) $c8 (p4.2-3) fine output gain 1 and fine output gain 2 bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 p4.2 0 0 fine output gain 1 (unsigned integer) p4.3 0 0 fine output gain 2 (unsigned integer) gain = 20 log([32768-og]/32768)db. og is the unsigned integer value in the ?fine output gain? field. fine output gain adjustment should be kept within t he range 0db to -3.5db. this adjustment occurs before the coarse output gain adjustment (register $b0). alteration of fine output gain 1 will affect the gain of both mod1 and audio outputs. $c8 (p4.4-5) output 1 offset and output 2 offset bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 p4.4 0 0 2?s complement offs et for mod1, resolution = av dd / 65536 per lsb p4.5 0 0 2?s complement offset for mod2, resolution = av dd / 65536 per lsb the programmed value is subtracted from the out put signal. can be used to compensate for inherent offsets in the output path via mod1 (output 1 offs et) and mod2 (output 2 offset). it is recommended that the offset correction is kept within the range +/-50mv. this adjustment occurs before the coarse output gain adjustment (register $b0), therefore an alteration to the latter register will require a compensation to be made to the output offsets. $c8 (p4.6) ramp rate control bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 p4.6 0 0 ramp rate up control ( rru) ramp rate down control (rrd) the ramp-up and ramp-down rates can be independently programmed. the ramp rates apply to all the analogue output ports. they only affect those ports bei ng turned on (ramp-up) or turned off (ramp down). the ramp rates should be programmed before ramping any outputs. time to ramp-up to full gain = (1 + rru) 1.333ms time to ramp down to zero gain = (1 + rrd) 1.333ms ramp up starts from when the transmit mode starts (mode control register $c1:b1 set to 1). ramp down starts from when transmit mode is turned off (mode control register $c1:b1 cleared to 0). $c8 (p4.7) transmit limiter control bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 p4.7 0 0 limiter setting this unsigned number sets the clipping point (maximum deviation from the centre value) for the mod1 and mod2 pins. the maximum setting ($3fff) is v bias (av dd /2) i.e. output limited from 0 to av dd . for an av dd of 3.3v, the resolution is approx. 0.3mv per lsb.
marine vhf audio and signalling processor CMX885 limiter threshold v p4.7 0 500 1000 1500 2000 2500 0 1000 2000 3000 4000 5000 6000 7000 8000 p4.7 value (decimal) pk-pk output level (mv) limit figure 15 limiter values the limiter is set to maximum following a c-bus reset or a power-up reset. the levels of internally generated signals may need to be adjusted by setting appropr iate transmit levels to avoid unintentional limiting. $c8 (p4.8) scrambler inversion frequency bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 p4.8 0 0 scrambler inversion frequency = f / 0.7324 this unsigned hex number sets the inversion fr equency for the voice scrambler and de-scrambler (default is 3300hz). $c8 (p4.9) audio filter sequence bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 p4.9 0 0 limit src input agc pre-emp 0 0 scramble 300hz b13 sets the position of the limiter in the audio processing chain. the default is a soft limiter function; setting this bit provides a hard limiter function. b12 sets the source of the reference signal when inputagc function is active. 0 = audio input 1 = pre-emphasis output b11-8 control the hardware inputagc function and its release timer for voice / audio signals on input 1 in 64ms steps: 0000 inputagc off 0001 inputagc on, release time = 64ms 0010 inputagc on, release time = 128ms 0011 inputagc on, release time = 196ms 0100 inputagc on, release time = 256ms 0101 inputagc on, release time = 320ms - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1111 inputagc on, release time = 960ms ? cml microsystems plc 56 2010 d/885/3
marine vhf audio and signalling processor CMX885 b7-0 set the order of the audio filter processing. th is feature can be used to optimise the signal to noise performance of particular radio hardware designs. each filter/process block can be specified in any order. each two-bit field specifies the order in which the process will be executed in tx mode, therefore it is imperative that each set of bit fields be different. the reverse sequence is used in rx mode. the voice filter and soft limiter will always be implement ed as the final block in the tx sequence. the default settings are: o pre-emp: 00 o scramble: 10 o 300hz hpf: 11 which will implement the line-up as shown in figure 16 and figure 17 : pre-emph (optional) scrambler (optional) voice lpf & soft limiter 300hz filter audio in + ctcss figure 16 default tx audio filter line-up discrim 300hz filter de-scrambler (optional) de-emph (optional) audio voice lpf figure 17 default rx audio filter line-up an alternative, preferred, line-up is shown in figure 18 and figure 19 , for the following settings: (p4.9 = $004b): o pre-emp: 01 o scramble: 10 o 300hz hpf: 11 pre-emph (optional) scrambler (optional) voice lpf & soft limiter 300hz filter audio in figure 18 preferred tx audio filter line-up discrim de-emph (optional) 300hz filter de-scrambler (optional) audio voice lpf figure 19 preferred rx audio filter line-up ? cml microsystems plc 57 2010 d/885/3
marine vhf audio and signalling processor CMX885 ? cml microsystems plc 58 2010 d/885/3 $c8 (p4.10) reserved ? do not use bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 p4.10 0 0 reserved ? set to $0608 reserved ? set to $0608 $c8 (p4.11) input agc threshold level bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 p4.11 0 0 threshold setting, resolution = av dd /16384 per lsb this unsigned number sets the threshold point (maximum deviation from the centre value) for the input agc function, where the input gain will be stepped to avoid exceeding the s pecification limits. the threshold is set to half of full-scale ($0fff = v bias (av dd /4)) following a c-bus reset or a power- up reset. 8.2.6 initialisation of the program blocks removal of the signal processing block from reset (power down register, $c0:b5 1 0 transition), with b4 kept low (= 0), will cause all of the program blocks (p0 ? p4) to be reset to their default values.
marine vhf audio and signalling processor CMX885 ? cml microsystems plc 59 2010 d/885/3 9 performance specification 9.1 electrical performance 9.1.1 absolute maximum ratings exceeding these maximum ratings can result in damage to the device. min. max. unit supply: dv dd - dv ss ? 0.3 4.5 v av dd - av ss ? 0.3 4.5 v voltage on any pin to dv ss ? 0.3 dv dd + 0.3 v voltage on any pin to av ss ? 0.3 av dd + 0.3 v current into or out of any power supply pin (excluding vbias) (i.e. vdec, avdd, avss, dvdd, dvss ) ? 30 +30 ma current into or out of any other pin ? 20 +20 ma voltage differential between power supplies: dv dd and av dd 0 0.3 v dv ss and av ss 0 50 mv q3 package (48-pin vqfn) min. max. unit total allowable power dissipation at tamb = 25c ? 1750 mw ... derating ? 17.5 mw/c storage temperature ? 55 +125 c operating temperature ? 40 +85 c l4 package (48-pin lqfp) min. max. unit total allowable power dissipation at tamb = 25c ? 1600 mw ... derating ? 16 mw/c storage temperature ? 55 +125 c operating temperature ? 40 +85 c 9.1.2 operating limits correct operation of the device outsi de these limits is not implied. notes min. max. unit supply voltage: dv dd ? dv ss 3.0 3.6 v av dd ? av ss 3.0 3.6 v v dec ? dv ss 12 2.25 2.75 v operating temperature ? 40 +85 c xtal/clk frequency (using a xtal) 11 3.0 12.288 mhz xtal/clk frequency (using an external clock) 11 3.0 24.576 mhz notes: 11 nominal xtal/clk frequency is 3.6864mhz. 12 the v dec supply is automatically created from dv dd by the on-chip voltage regulator.
marine vhf audio and signalling processor CMX885 ? cml microsystems plc 60 2010 d/885/3 9.1.3 operating characteristics for the following conditions unless otherwise specified: external components as recommended in figure 2 . maximum load on digital outputs = 30pf. xtal frequency = 3.6864mhz 0.01% (100ppm); tamb = ? 40c to +85c. av dd = dv dd = 3.0v to 3.6v. reference signal level = 308mv rms at 1khz with av dd = 3.3v. signal levels track with supply voltage, so scale accordingly. signal to noise ratio (snr) in bit rate bandwidth. input stage gain = 0db. output stage attenuation = 0db. dc parameters notes min. typ. max. unit supply current 21 all powersaved di dd (dv dd = 3.3v, v dec = 2.5v) ? 8 100 a ai dd (av dd = 3.3v) ? 4 20 a idle mode 22 di dd (dv dd = 3.3v, v dec = 2.5v) ? 1.12 ? ma ai dd (av dd = 3.3v) ? 50 ? a rx mode 22 di dd (dv dd = 3.3v, v dec = 2.5v) ? 5.00 ? ma ai dd (av dd = 3.3v) ? 3.20 ? ma tx mode 22 di dd (dv dd = 3.3v, v dec = 2.5v) ? 5.75 ? ma ai dd (av dd = 3.3v) 24 ? 3.20 ? ma additional current for auxiliary adc di dd (dv dd = 3.3v, v dec = 2.5v) ? 50 ? a additional current for each auxiliary dac ai dd (av dd = 3.3v) ? 200 ? a notes: 21 tamb = 25c. not including any current dr awn from the device pins by external circuitry. 22 auxiliary circuits disabled, bias enabled. 24 single mod output enabled.
marine vhf audio and signalling processor CMX885 ? cml microsystems plc 61 2010 d/885/3 dc parameters (continued) notes min. typ. max. unit xtal/clk 25 input logic 1 70% ? ? dv dd input logic 0 ? ? 30% dv dd input current (vin = dv dd ) ? ? 40 a input current (vin = dv ss ) ? 40 ? ? a c-bus interface and logic inputs input logic 1 70% ? ? dv dd input logic 0 ? ? 30% dv dd input leakage current (logic 1 or 0) 21 ? 1.0 ? 1.0 a input capacitance ? ? 7.5 pf c-bus interface and logic outputs output logic 1 (i oh = 120a) 90% ? ? dv dd (i oh = 1ma) 80% ? ? dv dd output logic 0 (i ol = 360a) ? ? 10% dv dd (i ol = -1.5ma) ? ? 15% dv dd ?off? state leakage current 21 ? ? 10 a irqn (vout = dv dd ) ? 1.0 ? +1.0 a rdata (output hiz) ? 1.0 ? +1.0 a v bias 26 output voltage offset wrt av dd /2 (i ol < 1 a) ? 2% ? av dd output impedance ? 22 ? k notes: 25 characteristics when driving the xtal/clk pin with an external clock source. 26 applies when utilising v bias to provide a reference voltage to other parts of the system. when using v bias as a reference, v bias must be buffered. v bias must always be decoupled with a capacitor as shown in figure 2 .
marine vhf audio and signalling processor CMX885 ? cml microsystems plc 62 2010 d/885/3 ac parameters (continued) notes min. typ. max. unit xtal/clk input ?high? pulse width 31 15 ? ? ns ?low? pulse width 31 15 ? ? ns input impedance (measured at 6.144mhz) powered-up resistance ? 150 ? k capacitance ? 20 ? pf powered-down resistance ? 300 ? k capacitance ? 20 ? pf xtal start up (from powersave) ? 400 ? ms v bias start up time (from powersave) ? 30 ? ms microphone, alternative and discriminator inputs (micn, altn, discn) input impedance 34 ? 1 ? m maximum input level (pk-pk) 35 ? ? 80% av dd load resistance (feedback pins) 80 ? ? k amplifier open loop voltage gain ? (i/p = 1mv rms at 100hz) ? ? 60 ? db unity gain bandwidth ? 1.0 ? mhz programmable input gain stage 36 gain (at 0db) 37 ? 0.5 0 +0.5 db cumulative gain error ? (wrt attenuation at 0db) ? 37 ? 1.0 0 +1.0 db notes: 31 timing for an external input to the xtal/clk pin. 34 with no external components connected. 35 centred about av dd /2; after multiplying by the gain of input circuit (with external components connected). 36 gain applied to signal at output of bu ffer amplifier: discfb, altfb or micfb 37 design value for this block only in test mode. overall attenuation input to output has a tolerance of 0db 1.0db.
marine vhf audio and signalling processor CMX885 ? cml microsystems plc 63 2010 d/885/3 ac parameters (continued) notes min. typ. max. unit modulator outputs 1/2 and audio output (mod1, mod2, audio) power-up to output stable 41 ? 50 100 s modulator attenuators attenuation (at 0db) 43 ? 1.0 0 +1.0 db cumulative attenuation error ? (wrt attenuation at 0db) ? ? 0.6 0 +0.6 db output impedance ? enabled 42 ? 600 ? ? disabled 42 ? 500 ? k output current range (av dd = 3.3v) ? ? 125 a output voltage range 44 0.5 ? av dd ?0.5 v load resistance 20 ? ? k audio attenuator attenuation (at 0db) 43 ? 1.0 0 +1.0 db cumulative attenuation error ? (wrt attenuation at 0db) ? ? 1.0 0 +1.0 db output impedance ? enabled 42 ? 600 ? ? disabled 42 ? 500 ? k output current range (av dd = 3.3v) ? ? 125 a output voltage range 44 0.5 ? av dd ?0.5 v load resistance 20 ? ? k notes: 41 power-up refers to issuing a c-bus command to turn on an output. these limits apply only if v bias is on and stable. at power s upply switch-on, the default state is for all blocks, except the xtal and c-bus interface, to be placed in powersave mode. 42 small signal impedance, at av dd = 3.3v and tamb = 25c. 43 with respect to the signal at t he feedback pin of the selected input port. 44 centred about av dd /2; with respect to the output driving a 20k load to av dd /2.
marine vhf audio and signalling processor CMX885 ? cml microsystems plc 64 2010 d/885/3 ac parameters (continued) notes min. typ. max. unit auxiliary signal inputs (aux adc 1) source output impedance 51 ? ? 24 k auxiliary 10 bit adc resolution ? 10 ? bits maximum input level (pk-pk) 54 ? ? 80% av dd conversion time 52 ? 250 ? s input impedance resistance ? 10 ? m capacitance ? 5 ? pf zero error ? (input offset to give adc output = 0) ? 0 ? 10 mv integral non-linearity ? ? 3 lsbs differential non-linearity 53 ? ? 1 lsbs auxiliary 10 bit dacs resolution ? 10 ? bits maximum output level (pk-pk), no load 54 80% ? ? av dd zero error ? (output offset from a dac input = 0) ? 0 ? 10 mv resistive load 5 ? ? k integral non-linearity ? ? 4 lsbs differential non-linearity 53 ? ? 1 lsbs notes: 51 denotes output impedance of the driver of the auxiliary input signal, to ensure < 1 bit additional error under nominal conditions. 52 with an auxiliary clock frequency of 3.6864mhz. 53 guaranteed monotonic with no missing codes. 54 level centered about av dd /2.
marine vhf audio and signalling processor CMX885 ? cml microsystems plc 65 2010 d/885/3 9.1.4 parametric performance for the following conditions unless otherwise specified: external components as recommended in figure 2 . maximum load on digital outputs = 30pf. xtal frequency = 3.6864mhz 0.003% (30ppm) ; tamb = ? 40c to +85c. av dd = dv dd = 3.0v to 3.6v. reference signal level = 308mvrms at 1khz with av dd = 3.3v. signal levels track with supply voltage, so scale accordingly. signal to noise ratio (snr) in bit rate bandwidth. input stage gain = 0db, out put stage attenuation = 0db. ac parameters notes min. typ. max. unit dsc decoder signal input dynamic range 81 100 ? 800 mvrms bit error rate (snr = 8db) 81 ? <1 ? 10 -2 co-channel rejection ? 10 ? db bit rate sync time ? 2 ? edges dtmf decoder sensitivity ? ? 22 +3 db response time ? 35 ? ms de-response time ? ? 45 ms falsing rate (per 30min voice input) ? 10 ? frequency tolerance ? 2.5 ? % twist ? 10 ? +10 db nwr decoder sensitivity ? tbd ? db inband tone encoder frequency range 288 ? 3000 hz tone frequency accuracy ? ? 0.3 % tone amplitude tolerance 83 ? 1.0 0 +1.0 db total harmonic distortion 82 ? 2.0 4.0 % dtmf encoder output signal level 84 ? 775 ? mvrms output level variation ? 0.5 ? db output distortion ? ? 5 % dsc encoder output signal level ? 775 ? mvrms output distortion ? ? 5 % 3 rd harmonic distortion ? ? 3 % logic 1 frequency ? 1300 ? hz logic 0 frequency ? 2100 ? hz baud rate ? 1200 ? bps pre-emphasis (per octave) ? 6 ? db notes: to meet dsc specifications, a 30ppm xtal, or better, is required. 81 av dd = 3.3v, for a ?101010101 ? 01? pattern measured at the input amplifier feedback pin. signal level scales with av dd . 82 measured at mod1 or mod2 output. 83 av dd = 3.3v and tx audio level set to 871mv p-p (308mvrms). 84 av dd = 3.3v. measured in single tone mode, p1.0 set to $2ffe.
marine vhf audio and signalling processor CMX885 ? cml microsystems plc 66 2010 d/885/3 ac parameters (continued) notes min. typ. max. unit analogue channel audio filtering pass-band (nominal bandwidth): received audio 91 300 ? 3300 hz 12.5khz channel transmitted audio 92 300 ? 2550 hz 25khz channel transmitted audio 93 300 ? 3000 hz pass-band gain (at 1.0khz) ? 0 ? db pass-band ripple (wrt gain at 1.0khz) ? 2.0 0 +0.5 db stop-band attenuation 33.0 ? ? db residual hum and noise tx 96 ? ? 47 ? dbm residual hum and noise rx 96 ? ? 74 ? dbm pre-emphasis 94 ? +6 ? db/oct de-emphasis 95 ? ? 6 ? db/oct audio scrambler inversion frequency ? 3300 ? hz passband 300 ? 3000 hz notes: 91 the receiver audio filter complies with the characteristic shown in figure 6 . the high pass filtering removes sub- audio components from the audio signal. 92 the 12.5khz channel filter complies with the characteristic shown in figure 9 . 93 the 25khz channel filter complies with the characteristic shown in figure 8 . 94 the pre-emphasis filter complies with the characteristic shown in figure 10 . 95 the de-emphasis filter complies wi th the characteristic shown in figure 7 . 96 psophometrically weighted. pre/de-emphas is and 25khz channel filter selected.
marine vhf audio and signalling processor CMX885 9.2 c-bus timing figure 20 c-bus timing c-bus timing notes min. typ. max. unit t cse csn enable to sclk high time 100 ? ? ns t csh last sclk high to csn high time 100 ? ? ns t loz sclk low to rdata output enable time 0.0 ? ? ns t hiz csn high to rdata high impedance ? ? 1.0 s t csoff csn high time between transactions 1.0 ? ? s t nxt inter-byte time 200 ? ? ns t ck sclk cycle time 200 ? ? ns t ch sclk high time 100 ? ? ns t cl sclk low time 100 ? ? ns t cds cdata setup time 75 ? ? ns t cdh cdata hold time 25 ? ? ns t rds rdata setup time 50 ? ? ns t rdh rdata hold time 0 ? ? ns notes: 1. depending on the command, 1 or 2 bytes of cdata are transmitted to the peripheral msb (bit 7) first, lsb (bit 0) las t. rdata is read from the peripher al msb (bit 7) first, lsb (bit 0) last. 2. data is clocked into the peripheral on the rising sclk edge. 3. commands are acted upon at the end of each command (rising edge of csn). 4. to allow for differing c serial interface formats, c-bus compatible ics are able to work with sclk pulses starting and ending at either polarity. 5. maximum 30pf load on irqn pin and each c-bus interface line. these timings are for the latest version of c-bus and allow faster transfers than the original c-bus timing specification. the CMX885 can be used in conj unction with devices that comply with the slower timings, subject to system throughput constraints. ? cml microsystems plc 67 2010 d/885/3
marine vhf audio and signalling processor CMX885 9.3 packaging figure 21 mechanical outline of 48-pin vqfn (q3) order as part no. CMX885q3 figure 22 mechanical outline of 48-pin lqfp (l4) order as part no. CMX885l4 as package dimensions may change after publication of this datasheet, it is recommended that you check for the latest packaging information from the data sheet page of the cml webs ite: [www.cmlmicro.com]. ? cml microsystems plc 68 2010 d/885/3
marine vhf audio and signalling processor CMX885 handling precautions: this product includes input protection, however, precautions should be taken to prevent device damage from electro-static discharge. cml does not assume any responsibility for the use of any circuitry described. no ipr or circu it patent licences are implied. cml reserves the right at any time without notice to change the said circuitry and this product specification. cml has a policy of test ing every product shipped using calibrated test equipment to ensure compliance with thi s product specification. specific testing of all circuit parameters is not necessarily performed.

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